PXIe-7966R with NI 5752 digitizer

[MansoorEE]

Hello, I am trying to achive 50 acquisitions of 10,000 samples with each acquisition 50us apart. Means that after the trigger, acquire 10,000 samples then wait 50us and acquire 10,000 samples and so on for 50 acquisition cycles. I need to acquire them on 16 channels. I have gone through the NI Examples ( NI 5752 Multi Record Digital Trigger.lvproj) and (NI 5752 Finite Acquisition Multiple Channels) so far. They are helpful but still I could not achive my goal.

Please help me out here.

[MansoorEE]

I am trying to achieve 50 acquisitions of 10,000 samples with each acquisition 50us apart. Means that after the trigger, acquire 10,000 samples then wait 50us and acquire 10,000 samples and so on for 50 acquisition cycles. I need to acquire them on 16 channels. I have modified the (NI 5752 Finite Acquisition Multiple Channels) example for NI PXIe 7966. If I set the FIFO size to 10,000 samples, it works but I can not force a delay of 50us between each acquisition. I have tested this project and seen that the minimum time between each acquisition is 100ms. And this is the normal time the Host vi takes to process the code.

The modified project is attached here. Can someone please help me out here?

[Dave.C]

Hi MansoorEE,

Could you tell us if you're getting any specific errors when you run the code?  Are you monitoring the timeouts on your FIFO writes?

Also, I don't see the FPGA VI in the project, could you attach it as well?

Thanks,

[David-A]

Hello Mansoor,

In the attached project you are loading the pre-compiled bitfiles onto your FPGA to perform the acquisition. To get the 50us pause between acuiqistion periods you would likely need to implement this with a few modications to the FPGA DAQ Mul Ch (FPGA).vi that is among the files you have attached (but curiously have left out of the project). Let me know if you would like to know what type of modifications would allow you to acquire at the desired rate, pause 50us, then resume acquisition.

On the Host side of things in the FPGA DAQ Mul Ch\FPGA DAQ Mul Ch (Host).vi I'm wondering why you put a while loop around everything. Currently the Open FPGA Reference, Abort method, Run method, and Close FPGA Reference are all inside of the while loop. By placing them inside the loop this means that you are retrieving a new reference, aborting execution (thus destorying any data that was in transit), starting the FPGA back up, then releasing the reference to the FPGA every time the loop iterates. You would likely want to move all of these portions of code outside of the while loop.

David A

[MansoorEE]

Thanks you David,

I have attached the whole project folder here. I did try moving things out of the  main while loop, but then I receive the following error

Error -50400 occurred at Invoke Method: FIFO.Read in FPGA DAQ Mul Ch 4 (Host).vi

Possible reason(s):

NI Platform Services:  The transfer did not complete within the timeout period or within the specified number of retries.

[Dave.C]

Hi MansoorEE,

The -50400 error you are seeing indicates that you are experiencing buffer underflow, or you are trying to read from it faster than elements are written.  The Avoiding Buffer Overflows in DMA Applications (FPGA  Module) document in the LabVIEW help provides some good information on how to address the error.  

Additionally, If you go to the LabVIEW Help Index and search for DMA (FPGA), there are some useful sections on best practices, buffers, determining the status, host VI designs, etc.  I think these might be helpful as well.

Finally, I would put an indicator on the line with the +1 function on it in the Acquisition FIFO write loop of the FPGA VI.  The way the code is currently, it looks to me like you will only read Num Samples samples and then be done in which case you will always go into the false case of the loop once that number of samples has been read.  Because the loop has no stop condition the FPGA code will remain in that loop forever always going to the false case.  Then when you try to read from a FIFO with no elements, it will time out resulting in the -50400 error.

Let us know if you have more questions, but I would start there.

Regards,

[MansoorEE]

Thank you Dave for your support. Let me try it. I will get back to you if I need more help.

[MansoorEE]

I need to use the TRIG connector on the NI PXIe - 8135 embedded controller to trigger the acquisiton. How can I do that?