Hello All,
I have a sine wave and a pulse coming from two (2) analog inputs A01 and A02 into a vi.
Once they are in the FPGA I also implemented a shift in phase by utilizing two 'Feedback nodes' with different delays at the same frequency.
However, if I increase the frequency of the second signal which is a pulse, several multiples of that occur which a specific phase of the cycle.
I tried to correct this using a positive zero crossing detection block but looks like my implementation is not right.
How do I fix this so that the only a single pulse will be generated regardless of the frequency of the signal. I have been thinking of being able to count the number of pulse generated and allowing just one pulse to pass rather than all but I also don't know how to convert this into a block.
Also the shape of the signals are distorted when visualized on waveform charts. I learned aliasing is the cause but don't know how to fix it. even though the signals appear fine on the oscilloscope.
Can someone help with this?
Images and code has been attached.
