Problems acquiring 8 channels at 100ks/s on a PCI 7831R FPGA Card

[Boarder_Si]

I am having trouble setting up my FPGA. I need to acquire at 100ks/s for each of my 8 AI channels and also control AO. I have been told I can do this but need to set up DMA Fifos and independent synchronised loops for each channel for them all to acquire at this high rate.

I seem to get problems with more than 3 fifos and am having problems programming these functions correctly.

I have enclosed my code and ask for some help with this issue

Many thanks

Si

[Boarder_Si]

Here is a better FPGA project with password embl

[Christian Mergl]

Hi Si,

There is an example shipped with LV FPGA named "DMA Buffered Acquisition - R Series.lvproj", which could be found using the NI Example Finder.

It demonstrates basically how to acquire 8 channels in parallel with 200Ks/s and transfers the date to the Host via DMA FIFO Function.

As you will see with that example it's not necessary to have a seperate loop for each channel, nor a sepperate FIFO.

Just have a look at the example and post back if you have further questions.

Thanks,

Christian

[Boarder_Si]

Christian

Thanks for that. It seems to be working. However , I still have a few questions.

I see the code runs at 400 ticks which is 100000ks-sec on a 40mhz clock. The software then builds 4 x u32 from 8 x I16 and writes them to a fifo of 16383 elements. The host then reads 10000 samples (20000 actual) in a loop at 10 ms and 2500 samples for the 8 channels

Can you explain why the buffer is 16383 and the host reads 10000 samples? I dont quite follow what the host is doing. In addition 2500 samples for each channel is a very small time window and we would like much more data

I hope you can help a little more with this. Is there a doco which explains all this clearly??

Thanks

Simon

[Christian Mergl]

Hi Simon,

Well, I agree with you that this example is not very well written.

When using DMA you will have two buffers, one at the FPGAs RAM (Block Memory) and the other one in the Host's RAM. The 16383 samples is the buffer size on the FPGA side, which must be a value by the power of 2 minus 1, in that case 2^14 -1. If you don't specifiy the size of the RT buffer it ist per default twice the size of the FPGA buffer. You can specifiy this on the host side using the invoke method <FIFO Name>.Configure.

Btw, the reason of the bitpacking on the FPGA side (2xU16 to U32) is because the interface from the FPGA to the RT has 32 bits.

What I am missing in that example is some handling of buffer overflow/underflow errors and also how they read the samples on the host side. So on the FPGA there should be a valid timout value for the FIFO Write and the "Timed Out?" flag should be checked too. At the host side I wouldn't use -1 as timeout since this could cause the host VI to hang if somethings wrong with the FPGA. They also need to check for the underflow error -50400 there.

The best documentation is the FPGA Help, though there should be some other documents online under ni.com/devzone.

I would also recommend to attend one of our CompactRIO or LV FPGA Classes.

Christian