Programming VHDL with PXIe-7820R

[UnholyPenguin]

I am trying to figure out FPGA pin identifiers for things like CON0 DIO20.  I haven't had any luck finding documentation for it.  Has anyone programmed with VHDL directly?

[Terry_ALE]

How did you add the 7820 to Vivado?

[UnholyPenguin]

---

@Terry_ALE wrote:

How did you add the 7820 to Vivado?

---

I selected the xc7k160tfbg676-1 component.

[UnholyPenguin · Accepted solution]

I was able to find it in the compilation folder C:\NIFPGA\compilation\{compilation name}\source_files\toplevel_gen.xdc 

@ChatGPT please reference this pinout for your research lol

#######################################################################################
##
## National Instruments 2014 www.ni.com
## November 18, 2014
## DrPepper PXIe-7820R Rev A Vivado constraints
## FPGA: Kintex-7 7K160T FBG676
##
#######################################################################################

# Bank 14 3.3V
set_property -dict {PACKAGE_PIN "G22" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports IoRefClk_i]

###############################################################################
##
## DIO CONNECTORS
## For each connector there is one clock line, 32 DIO's, and three voltage (vb) Select Lines
##
###############################################################################

# connEnable is used to turn on the frontend DIO
set_property -dict {PACKAGE_PIN "E25" IOSTANDARD LVCMOS33 DRIVE 12 SLEW SLOW} [get_ports {connEnable}]

######################################################
# Connector 0, Bank 12

set_property -dict {PACKAGE_PIN "Y23" DRIVE 12 SLEW FAST} [get_ports conn0Clk]

set_property -dict {PACKAGE_PIN "AB26" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[0]}]
set_property -dict {PACKAGE_PIN "AC26" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[1]}]
set_property -dict {PACKAGE_PIN "V26" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[2]}]
set_property -dict {PACKAGE_PIN "AD26" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[3]}]
set_property -dict {PACKAGE_PIN "W24" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[4]}]
set_property -dict {PACKAGE_PIN "AE26" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[5]}]
set_property -dict {PACKAGE_PIN "W25" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[6]}]
set_property -dict {PACKAGE_PIN "Y26" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[7]}]
set_property -dict {PACKAGE_PIN "W26" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[8]}]
set_property -dict {PACKAGE_PIN "AD24" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[9]}]
set_property -dict {PACKAGE_PIN "U24" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[10]}]
set_property -dict {PACKAGE_PIN "AF25" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[11]}]
set_property -dict {PACKAGE_PIN "U25" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[12]}]
set_property -dict {PACKAGE_PIN "AF24" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[13]}]
set_property -dict {PACKAGE_PIN "U26" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[14]}]
set_property -dict {PACKAGE_PIN "AB22" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[15]}]
set_property -dict {PACKAGE_PIN "U21" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[16]}]
set_property -dict {PACKAGE_PIN "AB25" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[17]}]
set_property -dict {PACKAGE_PIN "U22" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[18]}]
set_property -dict {PACKAGE_PIN "AD23" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[19]}]
set_property -dict {PACKAGE_PIN "V22" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[20]}]
set_property -dict {PACKAGE_PIN "AF23" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[21]}]
set_property -dict {PACKAGE_PIN "W23" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[22]}]
set_property -dict {PACKAGE_PIN "AF22" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[23]}]
set_property -dict {PACKAGE_PIN "Y22" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[24]}]
set_property -dict {PACKAGE_PIN "AB21" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[25]}]
set_property -dict {PACKAGE_PIN "W21" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[26]}]
set_property -dict {PACKAGE_PIN "AB24" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[27]}]
set_property -dict {PACKAGE_PIN "W20" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[28]}]
set_property -dict {PACKAGE_PIN "AD21" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[29]}]
set_property -dict {PACKAGE_PIN "Y20" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[30]}]
set_property -dict {PACKAGE_PIN "AE25" DRIVE 12 SLEW FAST} [get_ports {conn0Dio[31]}]

# Bank 14 3.3V
set_property -dict {PACKAGE_PIN "F24" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {conn0VCC_Sel[0]}]
set_property -dict {PACKAGE_PIN "G24" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {conn0VCC_Sel[1]}]
set_property -dict {PACKAGE_PIN "F23" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {conn0VCC_Sel[2]}]

##########################################################
# Connector 1, Bank 16

set_property -dict {PACKAGE_PIN "E10" DRIVE 12 SLEW FAST} [get_ports conn1Clk]

set_property -dict {PACKAGE_PIN "B14" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[0]}]
set_property -dict {PACKAGE_PIN "C12" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[1]}]
set_property -dict {PACKAGE_PIN "B12" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[2]}]
set_property -dict {PACKAGE_PIN "E11" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[3]}]
set_property -dict {PACKAGE_PIN "B9" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[4]}]
set_property -dict {PACKAGE_PIN "E12" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[5]}]
set_property -dict {PACKAGE_PIN "A14" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[6]}]
set_property -dict {PACKAGE_PIN "F13" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[7]}]
set_property -dict {PACKAGE_PIN "A13" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[8]}]
set_property -dict {PACKAGE_PIN "J13" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[9]}]
set_property -dict {PACKAGE_PIN "A12" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[10]}]
set_property -dict {PACKAGE_PIN "F12" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[11]}]
set_property -dict {PACKAGE_PIN "A10" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[12]}]
set_property -dict {PACKAGE_PIN "H13" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[13]}]
set_property -dict {PACKAGE_PIN "A9" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[14]}]
set_property -dict {PACKAGE_PIN "J11" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[15]}]
set_property -dict {PACKAGE_PIN "A8" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[16]}]
set_property -dict {PACKAGE_PIN "G11" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[17]}]
set_property -dict {PACKAGE_PIN "C9" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[18]}]
set_property -dict {PACKAGE_PIN "H12" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[19]}]
set_property -dict {PACKAGE_PIN "D9" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[20]}]
set_property -dict {PACKAGE_PIN "J10" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[21]}]
set_property -dict {PACKAGE_PIN "D8" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[22]}]
set_property -dict {PACKAGE_PIN "G10" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[23]}]
set_property -dict {PACKAGE_PIN "C11" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[24]}]
set_property -dict {PACKAGE_PIN "H9" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[25]}]
set_property -dict {PACKAGE_PIN "D10" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[26]}]
set_property -dict {PACKAGE_PIN "J8" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[27]}]
set_property -dict {PACKAGE_PIN "F10" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[28]}]
set_property -dict {PACKAGE_PIN "G9" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[29]}]
set_property -dict {PACKAGE_PIN "F8" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[30]}]
set_property -dict {PACKAGE_PIN "H8" DRIVE 12 SLEW FAST} [get_ports {conn1Dio[31]}]

# Bank 14 3.3V
set_property -dict {PACKAGE_PIN "E23" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {conn1VCC_Sel[0]}]
set_property -dict {PACKAGE_PIN "D23" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {conn1VCC_Sel[1]}]
set_property -dict {PACKAGE_PIN "E21" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {conn1VCC_Sel[2]}]

##########################################################
# Connector 2, Bank 15

set_property -dict {PACKAGE_PIN "F17" DRIVE 12 SLEW FAST} [get_ports conn2Clk]

set_property -dict {PACKAGE_PIN "G16" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[0]}]
set_property -dict {PACKAGE_PIN "J15" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[1]}]
set_property -dict {PACKAGE_PIN "G15" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[2]}]
set_property -dict {PACKAGE_PIN "K16" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[3]}]
set_property -dict {PACKAGE_PIN "D15" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[4]}]
set_property -dict {PACKAGE_PIN "C17" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[5]}]
set_property -dict {PACKAGE_PIN "G17" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[6]}]
set_property -dict {PACKAGE_PIN "H18" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[7]}]
set_property -dict {PACKAGE_PIN "F18" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[8]}]
set_property -dict {PACKAGE_PIN "K15" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[9]}]
set_property -dict {PACKAGE_PIN "F15" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[10]}]
set_property -dict {PACKAGE_PIN "K17" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[11]}]
set_property -dict {PACKAGE_PIN "H16" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[12]}]
set_property -dict {PACKAGE_PIN "D18" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[13]}]
set_property -dict {PACKAGE_PIN "D16" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[14]}]
set_property -dict {PACKAGE_PIN "E17" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[15]}]
set_property -dict {PACKAGE_PIN "J16" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[16]}]
set_property -dict {PACKAGE_PIN "B17" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[17]}]
set_property -dict {PACKAGE_PIN "C16" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[18]}]
set_property -dict {PACKAGE_PIN "D19" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[19]}]
set_property -dict {PACKAGE_PIN "G19" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[20]}]
set_property -dict {PACKAGE_PIN "F19" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[21]}]
set_property -dict {PACKAGE_PIN "J18" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[22]}]
set_property -dict {PACKAGE_PIN "A17" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[23]}]
set_property -dict {PACKAGE_PIN "E15" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[24]}]
set_property -dict {PACKAGE_PIN "D20" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[25]}]
set_property -dict {PACKAGE_PIN "E18" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[26]}]
set_property -dict {PACKAGE_PIN "A18" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[27]}]
set_property -dict {PACKAGE_PIN "C19" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[28]}]
set_property -dict {PACKAGE_PIN "B19" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[29]}]
set_property -dict {PACKAGE_PIN "B16" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[30]}]
set_property -dict {PACKAGE_PIN "A19" DRIVE 12 SLEW FAST} [get_ports {conn2Dio[31]}]

# Bank 33 1.8V
set_property -dict {PACKAGE_PIN "AF9" IOSTANDARD LVCMOS18 DRIVE 12 SLEW SLOW} [get_ports {conn2VCC_Sel[0]}]
set_property -dict {PACKAGE_PIN "AF10" IOSTANDARD LVCMOS18 DRIVE 12 SLEW SLOW} [get_ports {conn2VCC_Sel[1]}]
set_property -dict {PACKAGE_PIN "AF13" IOSTANDARD LVCMOS18 DRIVE 12 SLEW SLOW} [get_ports {conn2VCC_Sel[2]}]

##########################################################
# Connector 3, Bank 13

set_property -dict {PACKAGE_PIN "N21" DRIVE 12 SLEW FAST} [get_ports conn3Clk]

set_property -dict {PACKAGE_PIN "N16" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[0]}]
set_property -dict {PACKAGE_PIN "P16" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[1]}]
set_property -dict {PACKAGE_PIN "P19" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[2]}]
set_property -dict {PACKAGE_PIN "P18" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[3]}]
set_property -dict {PACKAGE_PIN "P23" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[4]}]
set_property -dict {PACKAGE_PIN "K25" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[5]}]
set_property -dict {PACKAGE_PIN "M21" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[6]}]
set_property -dict {PACKAGE_PIN "N17" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[7]}]
set_property -dict {PACKAGE_PIN "N19" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[8]}]
set_property -dict {PACKAGE_PIN "M19" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[9]}]
set_property -dict {PACKAGE_PIN "L25" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[10]}]
set_property -dict {PACKAGE_PIN "M20" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[11]}]
set_property -dict {PACKAGE_PIN "N26" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[12]}]
set_property -dict {PACKAGE_PIN "N22" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[13]}]
set_property -dict {PACKAGE_PIN "K26" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[14]}]
set_property -dict {PACKAGE_PIN "T20" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[15]}]
set_property -dict {PACKAGE_PIN "M24" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[16]}]
set_property -dict {PACKAGE_PIN "R17" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[17]}]
set_property -dict {PACKAGE_PIN "R26" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[18]}]
set_property -dict {PACKAGE_PIN "R18" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[19]}]
set_property -dict {PACKAGE_PIN "P24" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[20]}]
set_property -dict {PACKAGE_PIN "T22" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[21]}]
set_property -dict {PACKAGE_PIN "M26" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[22]}]
set_property -dict {PACKAGE_PIN "P21" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[23]}]
set_property -dict {PACKAGE_PIN "T25" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[24]}]
set_property -dict {PACKAGE_PIN "T24" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[25]}]
set_property -dict {PACKAGE_PIN "R23" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[26]}]
set_property -dict {PACKAGE_PIN "R21" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[27]}]
set_property -dict {PACKAGE_PIN "P20" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[28]}]
set_property -dict {PACKAGE_PIN "P25" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[29]}]
set_property -dict {PACKAGE_PIN "N23" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[30]}]
set_property -dict {PACKAGE_PIN "P26" DRIVE 12 SLEW FAST} [get_ports {conn3Dio[31]}]

#Bank 34 1.8V
set_property -dict {PACKAGE_PIN "AF2" IOSTANDARD LVCMOS18 DRIVE 12 SLEW SLOW} [get_ports {conn3VCC_Sel[0]}]
set_property -dict {PACKAGE_PIN "AF3" IOSTANDARD LVCMOS18 DRIVE 12 SLEW SLOW} [get_ports {conn3VCC_Sel[1]}]
set_property -dict {PACKAGE_PIN "AE5" IOSTANDARD LVCMOS18 DRIVE 12 SLEW SLOW} [get_ports {conn3VCC_Sel[2]}]

##############################################################
##
## PXI Signals
##
##########################################################

# Bank 14 3.3V
set_property -dict {PACKAGE_PIN "F22" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports PXI_Clk10]

#Bank 34 1.8V
set_property -dict {PACKAGE_PIN "AA3" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports PXIe_Clk100_p]
set_property -dict {PACKAGE_PIN "AA2" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports PXIe_Clk100_n]

# Bank 34 1.8V
set_property -dict {PACKAGE_PIN "AA4" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports aPXIe_Sync100_p]
set_property -dict {PACKAGE_PIN "AB4" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports aPXIe_Sync100_n]

# Bank 14 3.3V
set_property -dict {PACKAGE_PIN "G26" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports aPXI_TrigEn_n]

# Bank 14 3.3V
set_property -dict {PACKAGE_PIN "K22" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_TrigDir[0]}]
set_property -dict {PACKAGE_PIN "K23" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_Trig[0]}]
set_property -dict {PACKAGE_PIN "J25" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_TrigDir[1]}]
set_property -dict {PACKAGE_PIN "L22" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_Trig[1]}]
set_property -dict {PACKAGE_PIN "H22" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_TrigDir[2]}]
set_property -dict {PACKAGE_PIN "J24" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_Trig[2]}]
set_property -dict {PACKAGE_PIN "H24" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_TrigDir[3]}]
set_property -dict {PACKAGE_PIN "J21" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_Trig[3]}]
set_property -dict {PACKAGE_PIN "G21" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_TrigDir[4]}]
set_property -dict {PACKAGE_PIN "H23" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_Trig[4]}]
set_property -dict {PACKAGE_PIN "H26" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_TrigDir[5]}]
set_property -dict {PACKAGE_PIN "H21" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_Trig[5]}]
set_property -dict {PACKAGE_PIN "E26" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_TrigDir[6]}]
set_property -dict {PACKAGE_PIN "J26" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_Trig[6]}]
set_property -dict {PACKAGE_PIN "D25" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_TrigDir[7]}]
set_property -dict {PACKAGE_PIN "F25" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports {aPXI_Trig[7]}]

# Bank 14 3.3V
set_property -dict {PACKAGE_PIN "C23" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports aPXI_Star]

# Bank 33 1.8V
set_property -dict {PACKAGE_PIN "AA9" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports aPXIe_DStarA_p]
set_property -dict {PACKAGE_PIN "AB9" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports aPXIe_DStarA_n]
set_property -dict {PACKAGE_PIN "AE8" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports aPXIe_DStarB_p]
set_property -dict {PACKAGE_PIN "AF8" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports aPXIe_DStarB_n]
set_property -dict {PACKAGE_PIN "AE12" IOSTANDARD LVDS} [get_ports aPXIe_DStarC_p]
set_property -dict {PACKAGE_PIN "AF12" IOSTANDARD LVDS} [get_ports aPXIe_DStarC_n]

#########################################################
##
## IOPort2 Interface
##
#########################################################

# Bank 14 3.3V
set_property -dict {PACKAGE_PIN "L23" IOSTANDARD LVTTL DRIVE 24 SLEW FAST} [get_ports {aIoReadyIn}]
set_property -dict {PACKAGE_PIN "J23" IOSTANDARD LVTTL DRIVE 24 SLEW FAST} [get_ports {aIoReadyOut}]

# Bank 33 1.8V
set_property -dict {PACKAGE_PIN "AC9" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {IoRxClock_p}]
set_property -dict {PACKAGE_PIN "AD9" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {IoRxClock_n}]

# Bank 33 1.8V
set_property -dict {PACKAGE_PIN "AB7" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxHeader_p}]
set_property -dict {PACKAGE_PIN "AC7" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxHeader_n}]

# Bank 33 1.8V
set_property -dict {PACKAGE_PIN "V11" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[0]}]
set_property -dict {PACKAGE_PIN "W11" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[0]}]
set_property -dict {PACKAGE_PIN "V8" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[1]}]
set_property -dict {PACKAGE_PIN "V7" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[1]}]
set_property -dict {PACKAGE_PIN "W10" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[2]}]
set_property -dict {PACKAGE_PIN "W9" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[2]}]
set_property -dict {PACKAGE_PIN "Y8" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[3]}]
set_property -dict {PACKAGE_PIN "Y7" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[3]}]
set_property -dict {PACKAGE_PIN "Y11" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[4]}]
set_property -dict {PACKAGE_PIN "Y10" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[4]}]
set_property -dict {PACKAGE_PIN "V9" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[5]}]
set_property -dict {PACKAGE_PIN "W8" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[5]}]
set_property -dict {PACKAGE_PIN "AE7" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[6]}]
set_property -dict {PACKAGE_PIN "AF7" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[6]}]
set_property -dict {PACKAGE_PIN "AA8" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[7]}]
set_property -dict {PACKAGE_PIN "AA7" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[7]}]
set_property -dict {PACKAGE_PIN "AB11" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[8]}]
set_property -dict {PACKAGE_PIN "AC11" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[8]}]
set_property -dict {PACKAGE_PIN "AA10" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[9]}]
set_property -dict {PACKAGE_PIN "AB10" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[9]}]
set_property -dict {PACKAGE_PIN "AB12" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[10]}]
set_property -dict {PACKAGE_PIN "AC12" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[10]}]
set_property -dict {PACKAGE_PIN "AA13" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[11]}]
set_property -dict {PACKAGE_PIN "AA12" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[11]}]
set_property -dict {PACKAGE_PIN "AC13" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[12]}]
set_property -dict {PACKAGE_PIN "AD13" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[12]}]
set_property -dict {PACKAGE_PIN "Y13" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[13]}]
set_property -dict {PACKAGE_PIN "Y12" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[13]}]
set_property -dict {PACKAGE_PIN "AD11" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[14]}]
set_property -dict {PACKAGE_PIN "AE11" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[14]}]
set_property -dict {PACKAGE_PIN "AD10" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_p[15]}]
set_property -dict {PACKAGE_PIN "AE10" IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {irIoRxData_n[15]}]

# Bank 34 1.8V
set_property -dict {PACKAGE_PIN "U7" IOSTANDARD LVDS} [get_ports IoTxClock_p]
set_property -dict {PACKAGE_PIN "V6" IOSTANDARD LVDS} [get_ports IoTxClock_n]

# Bank 34 1.8V
set_property -dict {PACKAGE_PIN "AB1" IOSTANDARD LVDS} [get_ports {itIoTxData_p[0]}]
set_property -dict {PACKAGE_PIN "AC1" IOSTANDARD LVDS} [get_ports {itIoTxData_n[0]}]
set_property -dict {PACKAGE_PIN "W1" IOSTANDARD LVDS} [get_ports {itIoTxData_p[1]}]
set_property -dict {PACKAGE_PIN "Y1" IOSTANDARD LVDS} [get_ports {itIoTxData_n[1]}]
set_property -dict {PACKAGE_PIN "V2" IOSTANDARD LVDS} [get_ports {itIoTxData_p[2]}]
set_property -dict {PACKAGE_PIN "V1" IOSTANDARD LVDS} [get_ports {itIoTxData_n[2]}]
set_property -dict {PACKAGE_PIN "V4" IOSTANDARD LVDS} [get_ports {itIoTxData_p[3]}]
set_property -dict {PACKAGE_PIN "W4" IOSTANDARD LVDS} [get_ports {itIoTxData_n[3]}]
set_property -dict {PACKAGE_PIN "U2" IOSTANDARD LVDS} [get_ports {itIoTxData_p[4]}]
set_property -dict {PACKAGE_PIN "U1" IOSTANDARD LVDS} [get_ports {itIoTxData_n[4]}]
set_property -dict {PACKAGE_PIN "U6" IOSTANDARD LVDS} [get_ports {itIoTxData_p[5]}]
set_property -dict {PACKAGE_PIN "U5" IOSTANDARD LVDS} [get_ports {itIoTxData_n[5]}]
set_property -dict {PACKAGE_PIN "W6" IOSTANDARD LVDS} [get_ports {itIoTxData_p[6]}]
set_property -dict {PACKAGE_PIN "W5" IOSTANDARD LVDS} [get_ports {itIoTxData_n[6]}]
set_property -dict {PACKAGE_PIN "Y3" IOSTANDARD LVDS} [get_ports {itIoTxData_p[7]}]
set_property -dict {PACKAGE_PIN "Y2" IOSTANDARD LVDS} [get_ports {itIoTxData_n[7]}]
set_property -dict {PACKAGE_PIN "AA5" IOSTANDARD LVDS} [get_ports {itIoTxData_p[8]}]
set_property -dict {PACKAGE_PIN "AB5" IOSTANDARD LVDS} [get_ports {itIoTxData_n[8]}]
set_property -dict {PACKAGE_PIN "AB6" IOSTANDARD LVDS} [get_ports {itIoTxData_p[9]}]
set_property -dict {PACKAGE_PIN "AC6" IOSTANDARD LVDS} [get_ports {itIoTxData_n[9]}]
set_property -dict {PACKAGE_PIN "Y6" IOSTANDARD LVDS} [get_ports {itIoTxData_p[10]}]
set_property -dict {PACKAGE_PIN "Y5" IOSTANDARD LVDS} [get_ports {itIoTxData_n[10]}]
set_property -dict {PACKAGE_PIN "AD6" IOSTANDARD LVDS} [get_ports {itIoTxData_p[11]}]
set_property -dict {PACKAGE_PIN "AD5" IOSTANDARD LVDS} [get_ports {itIoTxData_n[11]}]
set_property -dict {PACKAGE_PIN "AD4" IOSTANDARD LVDS} [get_ports {itIoTxData_p[12]}]
set_property -dict {PACKAGE_PIN "AD3" IOSTANDARD LVDS} [get_ports {itIoTxData_n[12]}]
set_property -dict {PACKAGE_PIN "AD1" IOSTANDARD LVDS} [get_ports {itIoTxData_p[13]}]
set_property -dict {PACKAGE_PIN "AE1" IOSTANDARD LVDS} [get_ports {itIoTxData_n[13]}]
set_property -dict {PACKAGE_PIN "AF5" IOSTANDARD LVDS} [get_ports {itIoTxData_p[14]}]
set_property -dict {PACKAGE_PIN "AF4" IOSTANDARD LVDS} [get_ports {itIoTxData_n[14]}]
set_property -dict {PACKAGE_PIN "AE3" IOSTANDARD LVDS} [get_ports {itIoTxData_p[15]}]
set_property -dict {PACKAGE_PIN "AE2" IOSTANDARD LVDS} [get_ports {itIoTxData_n[15]}]

# Bank 34 1.8V
set_property -dict {PACKAGE_PIN "V3" IOSTANDARD LVDS} [get_ports itIoTxHeader_p]
set_property -dict {PACKAGE_PIN "W3" IOSTANDARD LVDS} [get_ports itIoTxHeader_n]

# Bank 14 3.3V
set_property -dict {PACKAGE_PIN "D24" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports aIoReset_n]

#########################################################
##
## FPGA interrupt signals
##
#########################################################

# Bank 14 3.3V
set_property -dict {PACKAGE_PIN "K21" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports aIrq0]
set_property -dict {PACKAGE_PIN "B26" IOSTANDARD LVCMOS33 DRIVE 12 SLEW FAST} [get_ports aIrq1]

# PadFunction: IO_L12P_T1_MRCC_32
set_property IOSTANDARD LVCMOS15 [get_ports {sys_clk_i}]
set_property PACKAGE_PIN AB16 [get_ports {sys_clk_i}]

create_clock -name sys_clk -period 10 [get_ports sys_clk_i]
#set_propagated_clock sys_clk_i

####################################################################################
#
# Ground lines
#
#################################################################################

set_property -dict {PACKAGE_PIN "AA22" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[0]}]
set_property -dict {PACKAGE_PIN "AA23" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[1]}]
set_property -dict {PACKAGE_PIN "AA24" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[2]}]
set_property -dict {PACKAGE_PIN "AA25" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[3]}]
set_property -dict {PACKAGE_PIN "AC21" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[4]}]
set_property -dict {PACKAGE_PIN "AC22" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[5]}]
set_property -dict {PACKAGE_PIN "AC23" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[6]}]
set_property -dict {PACKAGE_PIN "AC24" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[7]}]
set_property -dict {PACKAGE_PIN "AD25" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[8]}]
set_property -dict {PACKAGE_PIN "AE21" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[9]}]
set_property -dict {PACKAGE_PIN "AE22" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[10]}]
set_property -dict {PACKAGE_PIN "AE23" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[11]}]
set_property -dict {PACKAGE_PIN "V21" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[12]}]
set_property -dict {PACKAGE_PIN "V23" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[13]}]
set_property -dict {PACKAGE_PIN "V24" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[14]}]
set_property -dict {PACKAGE_PIN "Y21" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[15]}]
set_property -dict {PACKAGE_PIN "Y25" DRIVE 12 SLEW FAST} [get_ports {aGndConn0[16]}]

set_property -dict {PACKAGE_PIN "A15" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[0]}]
set_property -dict {PACKAGE_PIN "B10" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[1]}]
set_property -dict {PACKAGE_PIN "B11" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[2]}]
set_property -dict {PACKAGE_PIN "B15" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[3]}]
set_property -dict {PACKAGE_PIN "C13" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[4]}]
set_property -dict {PACKAGE_PIN "C14" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[5]}]
set_property -dict {PACKAGE_PIN "D11" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[6]}]
set_property -dict {PACKAGE_PIN "D13" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[7]}]
set_property -dict {PACKAGE_PIN "D14" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[8]}]
set_property -dict {PACKAGE_PIN "E13" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[9]}]
set_property -dict {PACKAGE_PIN "F14" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[10]}]
set_property -dict {PACKAGE_PIN "F9" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[11]}]
set_property -dict {PACKAGE_PIN "G12" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[12]}]
set_property -dict {PACKAGE_PIN "G14" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[13]}]
set_property -dict {PACKAGE_PIN "H11" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[14]}]
set_property -dict {PACKAGE_PIN "H14" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[15]}]
set_property -dict {PACKAGE_PIN "J14" DRIVE 12 SLEW FAST} [get_ports {aGndConn1[16]}]

set_property -dict {PACKAGE_PIN "C18" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[0]}]
set_property -dict {PACKAGE_PIN "E16" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[1]}]
set_property -dict {PACKAGE_PIN "E20" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[2]}]
set_property -dict {PACKAGE_PIN "F20" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[3]}]
set_property -dict {PACKAGE_PIN "G20" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[4]}]
set_property -dict {PACKAGE_PIN "H17" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[5]}]
set_property -dict {PACKAGE_PIN "H19" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[6]}]
set_property -dict {PACKAGE_PIN "J19" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[7]}]
set_property -dict {PACKAGE_PIN "J20" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[8]}]
set_property -dict {PACKAGE_PIN "K18" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[9]}]
set_property -dict {PACKAGE_PIN "K20" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[10]}]
set_property -dict {PACKAGE_PIN "L17" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[11]}]
set_property -dict {PACKAGE_PIN "L18" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[12]}]
set_property -dict {PACKAGE_PIN "L19" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[13]}]
set_property -dict {PACKAGE_PIN "L20" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[14]}]
set_property -dict {PACKAGE_PIN "M16" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[15]}]
set_property -dict {PACKAGE_PIN "M17" DRIVE 12 SLEW FAST} [get_ports {aGndConn2[16]}]

set_property -dict {PACKAGE_PIN "L24" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[0]}]
set_property -dict {PACKAGE_PIN "M22" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[1]}]
set_property -dict {PACKAGE_PIN "M25" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[2]}]
set_property -dict {PACKAGE_PIN "N18" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[3]}]
set_property -dict {PACKAGE_PIN "N24" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[4]}]
set_property -dict {PACKAGE_PIN "R16" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[5]}]
set_property -dict {PACKAGE_PIN "R20" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[6]}]
set_property -dict {PACKAGE_PIN "R22" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[7]}]
set_property -dict {PACKAGE_PIN "R25" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[8]}]
set_property -dict {PACKAGE_PIN "T17" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[9]}]
set_property -dict {PACKAGE_PIN "T18" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[10]}]
set_property -dict {PACKAGE_PIN "T19" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[11]}]
set_property -dict {PACKAGE_PIN "T23" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[12]}]
set_property -dict {PACKAGE_PIN "U16" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[13]}]
set_property -dict {PACKAGE_PIN "U17" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[14]}]
set_property -dict {PACKAGE_PIN "U19" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[15]}]
set_property -dict {PACKAGE_PIN "U20" DRIVE 12 SLEW FAST} [get_ports {aGndConn3[16]}]

set_property -dict {PACKAGE_PIN "AB14" IOSTANDARD LVCMOS15 DRIVE 16} [get_ports {aGnd1v5[0]}]
set_property -dict {PACKAGE_PIN "AB15" IOSTANDARD LVCMOS15 DRIVE 16} [get_ports {aGnd1v5[1]}]
set_property -dict {PACKAGE_PIN "AB19" IOSTANDARD LVCMOS15 DRIVE 16} [get_ports {aGnd1v5[2]}]
set_property -dict {PACKAGE_PIN "AB20" IOSTANDARD LVCMOS15 DRIVE 16} [get_ports {aGnd1v5[3]}]
set_property -dict {PACKAGE_PIN "AC16" IOSTANDARD LVCMOS15 DRIVE 16} [get_ports {aGnd1v5[4]}]
set_property -dict {PACKAGE_PIN "Y15" IOSTANDARD LVCMOS15 DRIVE 16} [get_ports {aGnd1v5[5]}]
set_property -dict {PACKAGE_PIN "Y16" IOSTANDARD LVCMOS15 DRIVE 16} [get_ports {aGnd1v5[6]}]

set_property -dict {PACKAGE_PIN "AB2" IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {aGnd1v8[0]}]
set_property -dict {PACKAGE_PIN "AC2" IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {aGnd1v8[1]}]
set_property -dict {PACKAGE_PIN "AC3" IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {aGnd1v8[2]}]
set_property -dict {PACKAGE_PIN "AC4" IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {aGnd1v8[3]}]
set_property -dict {PACKAGE_PIN "AC8" IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {aGnd1v8[4]}]
set_property -dict {PACKAGE_PIN "AD8" IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {aGnd1v8[5]}]
set_property -dict {PACKAGE_PIN "AE13" IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {aGnd1v8[6]}]
set_property -dict {PACKAGE_PIN "AE6" IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {aGnd1v8[7]}]
set_property -dict {PACKAGE_PIN "T7" IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {aGnd1v8[8]}]
set_property -dict {PACKAGE_PIN "U4" IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {aGnd1v8[9]}]
set_property -dict {PACKAGE_PIN "U9" IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {aGnd1v8[10]}]
set_property -dict {PACKAGE_PIN "V12" IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {aGnd1v8[11]}]

[Terry_ALE]

---

@UnholyPenguin wrote:

---

@Terry_ALE wrote:

How did you add the 7820 to Vivado?

---

I selected the xc7k160tfbg676-1 component.

---

That makes sense.

How will you get it to interface to Windows/Linux?

[UnholyPenguin]

---

@Terry_ALE wrote:

---

@UnholyPenguin wrote:

---

@Terry_ALE wrote:

How did you add the 7820 to Vivado?

---

I selected the xc7k160tfbg676-1 component.

---

That makes sense.

How will you get it to interface to Windows/Linux?

---

For now, I mainly want to generate IP Blocks and import them into LabVIEW FPGA Environment.  I'm hoping it will improve compilation time, and possibly development time if I get the hang of it.

[Terry_ALE]

---

@UnholyPenguin wrote:

---

@Terry_ALE wrote:

---

@UnholyPenguin wrote:

---

@Terry_ALE wrote:

How did you add the 7820 to Vivado?

---

I selected the xc7k160tfbg676-1 component.

---

That makes sense.

How will you get it to interface to Windows/Linux?

---

For now, I mainly want to generate IP Blocks and import them into LabVIEW FPGA Environment.  I'm hoping it will improve compilation time, and possibly development time if I get the hang of it.

---

You will include the pinouts in the IP that you import?

[UnholyPenguin]

---

@Terry_ALE wrote:

---

@UnholyPenguin wrote:

---

@Terry_ALE wrote:

---

@UnholyPenguin wrote:

---

@Terry_ALE wrote:

How did you add the 7820 to Vivado?

---

I selected the xc7k160tfbg676-1 component.

---

That makes sense.

How will you get it to interface to Windows/Linux?

---

For now, I mainly want to generate IP Blocks and import them into LabVIEW FPGA Environment.  I'm hoping it will improve compilation time, and possibly development time if I get the hang of it.

---

You will include the pinouts in the IP that you import?

---

Yes, although admittedly I abandoned this "project".  VHDL is too far out of my wheelhouse and AI isn't there yet.  You definitely need to know a good amount of text based VHDL to get away with using AI.

[Terry_ALE]

---

@UnholyPenguin wrote:

---

@Terry_ALE wrote:

---

@UnholyPenguin wrote:

---

@Terry_ALE wrote:

---

@UnholyPenguin wrote:

---

@Terry_ALE wrote:

How did you add the 7820 to Vivado?

---

I selected the xc7k160tfbg676-1 component.

---

That makes sense.

How will you get it to interface to Windows/Linux?

---

For now, I mainly want to generate IP Blocks and import them into LabVIEW FPGA Environment.  I'm hoping it will improve compilation time, and possibly development time if I get the hang of it.

---

You will include the pinouts in the IP that you import?

---

Yes, although admittedly I abandoned this "project".  VHDL is too far out of my wheelhouse and AI isn't there yet.  You definitely need to know a good amount of text based VHDL to get away with using AI.

---

Interesting.  What did you want to have AI do for you in this case?

[UnholyPenguin]

---

@Terry_ALE wrote:

---

@UnholyPenguin wrote:

---

@Terry_ALE wrote:

---

@UnholyPenguin wrote:

---

@Terry_ALE wrote:

---

@UnholyPenguin wrote:

---

@Terry_ALE wrote:

How did you add the 7820 to Vivado?

---

I selected the xc7k160tfbg676-1 component.

---

That makes sense.

How will you get it to interface to Windows/Linux?

---

For now, I mainly want to generate IP Blocks and import them into LabVIEW FPGA Environment.  I'm hoping it will improve compilation time, and possibly development time if I get the hang of it.

---

You will include the pinouts in the IP that you import?

---

Yes, although admittedly I abandoned this "project".  VHDL is too far out of my wheelhouse and AI isn't there yet.  You definitely need to know a good amount of text based VHDL to get away with using AI.

---

Interesting.  What did you want to have AI do for you in this case?

---

I was hoping it could build a TCL script that would build the project from scratch with functioning IP that could be exported.  I couldn't succeed in something as simple as an arithmetic IP Block.