Q Encoder

[Ambrose1464]

I had given a task (picture) about the quadrature encoder. I have problem is how to simulate the A & B signal then using X1 decode?

Your helping is much appreciated.Thank you.

[RavensFan]

Please put a little more detail into your question.

First of all, include where LabVIEW fits into your question.

[RTSLVU]

Well in simple terms a quadrature encoder outputs two square waves with A or B leading by 90 degrees depending on the direction the encoder is spinning.

Seems trivial to simulate a couple square waves with one of them leading or lagging the other by 90 degrees. 

As you can see your X1 output is pulsed once when the leading square wave is high and the lagging is low

[Ambrose1464]

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@RTSLVU wrote:

Well in simple terms a quadrature encoder outputs two square waves with A or B leading by 90 degrees depending on the direction the encoder is spinning.

Seems trivial to simulate a couple square waves with one of them leading or lagging the other by 90 degrees. 

As you can see your X1 output is pulsed once when the leading square wave is high and the lagging is low

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But how i going to draw out the QE at my FPGA target? I need to acquire the channel A and B signal and the counter value from FPGA to Host PC. I totally no idea how to implement out the vi. I'm stuck here. 

[Ambrose1464]

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@RavensFan wrote:

Please put a little more detail into your question.

First of all, include where LabVIEW fits into your question.

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My question is how to implement out the channel A and B signal (either A leading B or B leading A can function both way) after that using X1 decode (this is at FPGA), from the Host PC i want acquire the channel A and B signal and the counter value from the FPGA. Finally display out the signal and the counter value on the Host PC. Currently I still have no idea how I going to generate the channel A and B signal.

[RavensFan]

Please give a complete story as to what you are trying to do.  Now you are talking about using an FPGA which you failed to mention in the original post.

Where does the FPGA fit into this?  Are you trying to take two digital inputs (Chan A and Chan B) into the FPGA then have the FPGA output 3 digital outpus (X1 X2 X4)?

What do you mean by "how to generate channel A and channel B"?  Those get generated by your encoder.

[Ambrose1464]

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@RavensFan wrote:

Please give a complete story as to what you are trying to do.  Now you are talking about using an FPGA which you failed to mention in the original post.

Where does the FPGA fit into this?  Are you trying to take two digital inputs (Chan A and Chan B) into the FPGA then have the FPGA output 3 digital outpus (X1 X2 X4)?

What do you mean by "how to generate channel A and channel B"?  Those get generated by your encoder.

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First i want to sorry about i din mention FPGA. I want to take digital input Channel A and B have 3 digital outputs X1, X2 X4. That I still have problem to build the encoder. No idea how to build out.  

[RavensFan]

The FPGA has nodes in it that allow it to detect a rising or falling edge.  I would set up a loop to detect a rising and falling edge on both Chan A and Chan B.  (with a zero timeout)

If any of the 4 are triggered, then you write a true to your X4 output.

If Chan A's rising edge is triggered Chan B is Low  OR  Chan B's Falling edge is triggered and Chan B is High , then write a  true to your X2 output.

If Chan A's rising edge is triggered Chan B is Low, then write a true to X1 output.

Now all of these pulses need to go back to false at some point of time.  Do you have a defined pulse width?  If so, then have them return to false after X amount of time has passed. But if the encoder is spinning to fast, you could wind up with another trigger point before the pulse has had enough time to remain high.  I don't know how you'd handle that.  I can only assume the parameters are such that you've specified a limit on how fast the encoder can be.

The pictures seem to give it a 50% duty cycle on X4.  But that doesn't seem like it would be accurate because the time between pulses is dependent on the speed of the encoder.  I have no idea the best way to handle that.

[RTSLVU]

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@Ambrose1464 wrote:

First i want to sorry about i din mention FPGA. I want to take digital input Channel A and B have 3 digital outputs X1, X2 X4. That I still have problem to build the encoder. No idea how to build out.  

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Here is a good place to start Encoder Measurements: How-To Guide

[Ambrose1464]

this is my vi. is it correct? This is my first try. The channel selection means can choose either A lead B or B lead A. Thank you very much.