Q Encoder

[Ambrose1464]

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@RavensFan wrote:

The FPGA has nodes in it that allow it to detect a rising or falling edge.  I would set up a loop to detect a rising and falling edge on both Chan A and Chan B.  (with a zero timeout)

If any of the 4 are triggered, then you write a true to your X4 output.

If Chan A's rising edge is triggered Chan B is Low  OR  Chan B's Falling edge is triggered and Chan B is High , then write a  true to your X2 output.

If Chan A's rising edge is triggered Chan B is Low, then write a true to X1 output.

Now all of these pulses need to go back to false at some point of time.  Do you have a defined pulse width?  If so, then have them return to false after X amount of time has passed. But if the encoder is spinning to fast, you could wind up with another trigger point before the pulse has had enough time to remain high.  I don't know how you'd handle that.  I can only assume the parameters are such that you've specified a limit on how fast the encoder can be.

The pictures seem to give it a 50% duty cycle on X4.  But that doesn't seem like it would be accurate because the time between pulses is dependent on the speed of the encoder.  I have no idea the best way to handle that.

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this is my vi. is it correct? This is my first try. The channel selection means can choose either A lead B or B lead A. Thank you very much.

[Ambrose1464]

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@RTSLVU wrote:

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@Ambrose1464 wrote:

First i want to sorry about i din mention FPGA. I want to take digital input Channel A and B have 3 digital outputs X1, X2 X4. That I still have problem to build the encoder. No idea how to build out.  

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Here is a good place to start Encoder Measurements: How-To Guide

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This page need to use hardware is it? I had seen before.  First I need to implement an vi first that without hardware and all the input and output function correctly.

[RavensFan]

So with this VI you want to GENERATE the signals on the A and B channels.

First glance, I think your boolean logic would work for alternating high and low pulses between the channels.

The flaw in your VI is that you will never write out those trues and falses to the digital outputs.  The loop runs forever and the digital outputs are outside of the loop.  The boolean values never reaach them.  bring the digital outputs into the loop.

[Ambrose1464]

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@RavensFan wrote:

So with this VI you want to GENERATE the signals on the A and B channels.

First glance, I think your boolean logic would work for alternating high and low pulses between the channels.

The flaw in your VI is that you will never write out those trues and falses to the digital outputs.  The loop runs forever and the digital outputs are outside of the loop.  The boolean values never reaach them.  bring the digital outputs into the loop.

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If i move the digital output inside the loop that mean 1 case have 2 output, i have 2 case total have 4 digital output is it? the 2 case is the A lead B and B lead A. this is my vi. Thank you.

[RavensFan]

Do you want to be able to change the channel selection (which I guess actually means direction) while the VI is running?  if so, your VI is inside out.

The case structure needs to be inside the loop..

If you move the digital outputs outside the loop, they will never execute because the loop never ends.  This is basic dataflow.  Do you really want two more digital output channels to be used in teh other case?

Attach a VI instead of pictures, I can then modify it to something that works in a more logical manner.

You can actually merge the last two frames of the sequence structure.  You probably don't need the sequence structure at all.

[Ambrose1464]

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@RavensFan wrote:

Do you want to be able to change the channel selection (which I guess actually means direction) while the VI is running?  if so, your VI is inside out.

The case structure needs to be inside the loop..

If you move the digital outputs outside the loop, they will never execute because the loop never ends.  This is basic dataflow.  Do you really want two more digital output channels to be used in teh other case?

Attach a VI instead of pictures, I can then modify it to something that works in a more logical manner.

You can actually merge the last two frames of the sequence structure.  You probably don't need the sequence structure at all.

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Here is my vi.  Thanks for your help. I'm really appreciated. 

[RavensFan]

Here is your VI modified to a more logical structure.  It will allow you to change direction while it is operating.  Basically be virtually swapping A and B channels in mid-stream,  And you are now down to a single set of LED's on the front panel and a single set of digital outputs for channel A and channel B.

[Ambrose1464]

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@RavensFan wrote:

Here is your VI modified to a more logical structure.  It will allow you to change direction while it is operating.  Basically be virtually swapping A and B channels in mid-stream,  And you are now down to a single set of LED's on the front panel and a single set of digital outputs for channel A and channel B.

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Thanks for your vi . How to implement the x1 decode ? because i want to acquire the signal channel a and b and the counter value from FPGA to pc. 

[RavensFan]

Look back at what I wrote up in an earlier message.

But I'm confused.  You set you wanted to read A and B to generate the X# channels.

Then you post a VI where you are generating A and B signals.

Now you are back to saying you want to acquire A and B signals and generate X1.

I feel like you still haven't clearly told the story of what you are actually trying to do.

[Ambrose1464]

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@RavensFan wrote:

Look back at what I wrote up in an earlier message.

But I'm confused.  You set you wanted to read A and B to generate the X# channels.

Then you post a VI where you are generating A and B signals.

Now you are back to saying you want to acquire A and B signals and generate X1.

I feel like you still haven't clearly told the story of what you are actually trying to do.

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Hi Raven, the final result i want is above diagram. this is what i want the result out. the above diagram will display the result on my host PC.