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Q: What causes unresponsive FPGA elements after restart?

Hey guys,

 

I'm at my wits end here trying to interface with an FPGA. I've currently got it configured as follows:

 

7813R FPGA card in a LV-RT machine, running LV2012 on host and Real-Time machines.

 

Compile: Run when loaded = True

Obtain Reference:

  • Linked to bitfile 
  • FPGA ref bound to typedef
  • Run the FPGA VI = False

FIFOs (2 host-to-target DMAs) depth initialized after reference obtained.

 

Code then utilises reference to read indicators, send values to FIFOs and update controls.

 

On Shutdown: FIFOs stopped, but reference not closed.

 

My problem: All subsequent runs after shutting down the program (via the shutdown method) will successfully obtain a reference to the FPGA and init FIFOs (no errors generate), but attempts to read any of the indicators, or update any of the controls do nothing. Indicators show default values, and controls are unresponsive. In the past, I've fixed this by recompiling the FPGA, also sometimes by just redownloading it. Since I made some changes to the way data is loaded into the FIFOs (absolutely no changes to anything that ever touched the FPGA reference, purely to the way the arrays are formatted), nothing I do seems to recover the responsiveness.

 

I've tried: Restarting the RT machine, re-downloading the FPGA (in different orders). I've added close FPGA reference and "Start on Run" to the obtain reference and then restarting and re-downloading. Absolutely nothing has worked. I'm currently in the process of removing "Run on load" (performing a recompile), after which I will add "Start on Run" back into the Obtain reference vi.

 

I'm at my wits end. Has anyone encountered this sort of problem before, does anyone know what causes it?

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Are you able to post your codes?

 

Does manually reading/writing to FPGA through NI Distributed System Manager show any responsiveness from your 7813R card?

 

Once I saw this happen when data structure on RT (which you're trying to share/read/write) didn't exactly match what was in FPGA bitfile.

 

-DP

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