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Question about reading resolvers

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Hi,

I hope you are doing well.

 

I am reading different Resolver(s) utilizing FPGA and simply put, excitation is sent out using an Analog output, resolver returns sine and cosine waveform which is captured using analog inputs.

After the positive zero crossing (- to +) of excitation signal, I am read sine and cosine values at Pi/2 (1/4th of period) and then I send this value to arctan2 function, later convert it to 0-360. All this is working fine but I realized that my readings are not consistent between different manufacturers. Comparison is done my reading the resolver mounted on a motor, motor is locked into a specific position where the electrical degree value should be x value in all quadrants. Example electrical degrees should be zero at 0,90,180,270 for a 4 pole motor.

I did take phase offset into consideration too but that did not improve the result. Maybe I did not understand that correctly, I can observe a phase difference between excitation signal and sine wave returned by resolver.

After several days of testing, I learned that in some resolver(s), the amplitude of sine and cosine do not match (at a point you can overlap them but they do not in my case) they are (most commonly) off by .05V at Pi/2 than what they should have been. Say for example cosine is supposed to be 0V but it is .05V and Sine is 1V. Cosine, goes to zero if I turn the resolver but then sine is not at 1V, it might be .95V.

 

All this made me doubt my code as I expect results to be consistent across different resolver manufacturers. I would really appreciate if someone has any suggestion.

Thank you for reading.

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Have you considered a dedicated analog/mixed-signal circuit for resolvers instead of implementing your own on FPGA?

https://www.analog.com/en/resources/analog-dialogue/articles/precision-rtdc-measures-angular-positio...

 

Santhosh
Soliton Technologies

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Hi Santosh,

 

Thank you for the suggestion, this is one restriction I have, I have to implement it on FPGA to keep the cost and chaos down. But if nothing improves, I might end up utilizing RTDC :). 

 

First I would like to exhaust all possibilities on FPGA.

 

x

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Try Resolver Signal Simulation and Measurement in LabVIEW FPGA ?

-------------------------------------------------------
Control Lead | Intelline Inc
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Hi ZYOng,

 

Thank you for your reply. I implemented the logic mentioned in the link, it works but not as good. The results are not as stable as I am getting with my method. Specially in a noisy environment.

 

I did some more reading on the link that Santosh provided and it called out the same issue I am experiencing, amplitude mismatch. I guess I need to somehow automatically & accurately identify it to make adjustments for it.

 

Xonmyth_0-1721922104202.png

 

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Solution
Accepted by topic author Xonmyth

See if this paper helps - https://jpels.org/digital-library/manuscript/file/17559/9-JPE-09-34.pdf

santo_13_0-1721924693283.png

 

Santhosh
Soliton Technologies

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Message 6 of 7
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Thank you! I will give it a read.

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