Question related to FPGA Timekeeper, TSN and accuracy between samples from multiple cRIO.

[Michel_Gauvin]

My goal is to determine the timing accuracy between the samples from one channel on cRIO #1 and the samples from one channel on cRIO #2 by injecting the same signal (60Hz) coming from a precision source (signal generator) and by synchronizing the samples using TSN.

I have two cRIO-9047 each containing a NI-9215 analog input module. Both cRIO are using TSN (time sensitive network), which I have validated that one is the master and the other a slave with the property “Selected?” set to true.  I’m using the FPGA Timekeeper library to synchronize the FPGA time with the RT time. I’m sampling at 50KS/s on the FPGA.

Both cRIO trigger their recording (1 second) based on the same threshold.  Timestamping is done at the FPGA level and timestamps and values are sent to the RT software which logs the timestamps and values in a database.

From the database I extract timestamps and values from both channels from the two cRIO. I must align timestamps to perform FFT and make a phase difference. For that I’m using this function “National Instruments\LabVIEW 2020\vi.lib\gmath\interp.llb\Interpolate 1D.vi”.

Based on the phase difference I’m observing a variation of 0.3us to 20us timing difference between the two waveform (I have performed several test).

Is this the expected accuracy using the TSN and FPGA Timekeeper ? If yes, it would be nice to find more information on what may cause this (I’m aware of the different ppm clock accuracy, the fpga 40MHz clock (25ns) and other information that can be found on NI but maybe I'm missing some of it).

I’m trying to find an explanation for this behavior and trying to see if I can get better results with some in-depth knowledge from NI or other poeple with this expertise (without using the GPS module).

I have attached the fpga code and rt, which are identical on both cRIO.

Thanks in advance.

Michel G.

[ZYOng]

What is the network topology?

Are two cRIO and the host PC connected to a TSN-enabled switch?

Or the cRIO connected to the host PC on eth0 and connected to each other on eth1?

[Michel_Gauvin]

1. Currently host PC connect to cRIO #1 eth0 and cRIO #2 eth1.

2. Both cRIO are connteced cRIO #1 eth1 (TSN slave) -> cRIO #2 eth0 (TSN master)

RT applications are running on both cRIO.

[PaulRB · Accepted solution]

I believe that all cRIO-904x and cRIO-905x controllers will synchronize most/all clocks on the system. So the FPGA and RTOS clocks are both automatically synced to network time without you having to do anything. There should be a handful of synchronization IO nodes on the FPGA that will allow you to get the current time, offset, sync status, etc. I would try removing all of the FPGA timekeeper code and use the IO nodes instead to see if you get better synchronization. With 2 cRIOs connected directly to each other, I would expect you to get <100nsec synchronization.

[Michel_Gauvin]

Hi Paul,

I didn't see that one coming.... simplicity !!!

I've done 10 measurements at 50KS/s and measurements from 2 cRIO are within 300 ns.

Thanks,

Michel G.