Questions about compiling the FPGA VI

[TCPIP]

  I have compiled the FPGA VI, in the first time, it compiled successfully, the compilation report shows that there is no overmapped of the resources,  but in the second time, i just REDUCE 1 + code, and the compilation report tells me that there is an overmapped of the resources, the resources overmapped is due to the over use of the LUT. In fact, I have used FIFO in the VI, but acutally, I set it to memory block type in the property setting, NOT LUT type. So I don't know why the resources of LUT is overmapped suddenly.

  And I have used 5 target scoped FIFO and 1 target to host FIFO.

  Will my situation improve if I change the type of the FIFO into the Flip Flop type?

  I have attached the compliation report of first time and second time.

  Thank you for your helping!

[BillMe]

Your problem is that the number of slices used is 99%. At this capacity, there's a good chance the compiler won't be able to place and route successfully. You were lucky in the first instance.

Whenever you get close to 90% capacity, you should either:

1) Take a look at your code and change it to make it more gate efficient  (read the error message and pay heed to the suggestions on how to lower your usage) or 2) Split the functionality up into more than one FPGA.

I don't think trying to figure out why one small change caused an unsuccessful compile when you're already at 99% capacity is worth the effort. If your application is that critical that it has to fit into one FPGA, you should be using traditional FPGA tools where you have more control over the constraints placed on the compiler.

My $0.02.