Questions about data storage and RAM resource usage in CompactRIO

[2528642245@qq.com]

First of all my device is a CRIO-9043.

I want to use one dimensional lookup table for interpolation in FPGA.vi, I am using U16 data type and one lookup table can store 40960 data and I need to store 7 million data. Currently I have inserted only 16 tables and the RAM resources are not enough. My compilation tells me that one lookup table takes up 19 RAM resources (my device has a total of 325 RAM resources).

But on the lookup table it shows that one table uses only 80KB of storage, while on the official website the CRIO-9043 has a RAM size of 2G!

I don't know how to solve this problem. Attached is my program, sorry it's only in Chinese!

[GerdW]

Hi 252,

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2528642245@qq.com wrote:

But on the lookup table it shows that one table uses only 80KB of storage, while on the official website the CRIO-9043 has a RAM size of 2G!

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Don't get confused about RAM (accessable by the CPU) and block memory (accessable by the FPGA)!

Your FPGA cannot access host RAM this easily…

Btw. did you read the datasheet&specs of your cRIO?

The FPGA can only handle 11,700kbits of block RAM! (= 1462.5 kByte ~= 18 tables of 80kB for optimal usage…)

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2528642245@qq.com wrote:

I want to use one dimensional lookup table for interpolation in FPGA.vi, I am using U16 data type and one lookup table can store 40960 data and I need to store 7 million data. Currently I have inserted only 16 tables and the RAM resources are not enough.

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Do you want to use "one lookup table"?

Do you want to use more than one table? How many?

Why do you need "7 million data" in your FPGA algorithm?

Please explain what your goal is and what your requirements are!

[2528642245@qq.com]

Hi GerdW,

First of all thank you very much for your reply, then I can understand that the 2G on the official website refers to the CRIO storage (which can be accessed by the CPU), while the FPGA has its own dedicated RAM (BRAM).Can I take it that way?

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Yes, I need to read the interpolated data through the CRIO on the RT side host.vi.

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Yes, I need more lookup tables, one lookup table can store 40960 data, I need to store 7 million.

My need is to get the interpolated value of its counterpart in the lookup table by constantly reading the collected signal value (similar to the address of a lookup table, but with a fractional part present). And as for the 7 million points I can't quite explain it, all I can say is that this much data is needed to accomplish this task.

So please, do you have a better way to accomplish this task of getting interpolated values? It may not need to be 7 million, I can reduce the number of values to be stored by simplifying the task.

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This is my program to get interpolation results by timed loops, since it's just a functional verification, I divide the number of loops by a factor instead of the acquired signal. But it can only run at a maximum loop rate of 250k, is there a better way to make it faster?

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I have a lot of questions, thank you for your answers and good luck with your life!

Please point out any inaccuracies or ambiguities in the translation.

Best regards,

252

[GerdW]

Hi 252,

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2528642245@qq.com wrote:

So please, do you have a better way to accomplish this task of getting interpolated values? It may not need to be 7 million, I can reduce the number of values to be stored by simplifying the task.

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Right now your VI already contains 15 tables of 40960 U16 value, so you reached nearly the allowed maximum of block RAM…

I see two options:

• Transfer the reading/sample to your cRIO host and do the scaling with your "7 million samples table" in the host!
• Reduce the number of tables or table size dramatically and do the interpolation in the FPGA.

Remember: FPGAs typically can do algorithms fast and at a determined speed, but they usually don't access large memory areas!