RS422 packet Loss when using 115200 buad rate and length 154 bytes, data rate of 20ms.

[sabah_TASL]

Hi Everybody,

I am trying to loop back between two PXI chassis, both chassis are having PXIe-8431 card (RS422/RS485). I am writing serial data packet of length 154 bytes at a buad rate of 115200 from chassis 1 at rate of 20ms (50Hz). When I try to receive serial data from other port in the chassis 2. I am not able to receive 154 bytes consistently.   

I am not using end termination character (0x0A), instead I have packet header (0x05,0x05,0x05,0x05). I have connected pin number (8,9) (Tx+,Tx-) of Chassis1 RS422 card to pin number (4,5) (Rx+,Rx-) of Chassis 2 RS422 card, Also both GND (Pin 1) are connected.

I have experimented the same exercise with 40ms data rate, and I receive 154 data byte consistently.

40ms.

20ms.

Please guide me in resolving the fluctuation in data byte read with a data rate of 20ms.

[UliB]

Simple solution: Do not use 'bytes at port'.

You know how many bytes you expect, so just wire a constant with 154 to 'byte count' of VISA read.

And I think you can delete VISA flush buffer too. 

Edit: And you do not need the 'Wait Until Next ms Multiple Function' node in the while loop. VISA Read will time the loop for you.

[RTSLVU]

Most serial communication issues can be solved by watching this video: VIWeek 2020/Proper way to communicate over serial

[sabah_TASL]

Actually I don't want my application to wait until I receive 154 bytes of data, I require my application to run exactly at 20 ms.

This problem doesn't occur when I loopback within same PXI chassis.

[crossrulz · Accepted solution]

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@sabah_TASL wrote:

Actually I don't want my application to wait until I receive 154 bytes of data, I require my application to run exactly at 20 ms.

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This is a case where your data source sets your application rate.  So as long as your first controller sends the data frame every 20ms, your second controller will get 154 bytes every 20ms.  They are directly linked as long as your do your communications properly.

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@sabah_TASL wrote:

This problem doesn't occur when I loopback within same PXI chassis.

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Of course it doesn't.  When in the same chassis, you have a synchronous operation as the Write has to complete before the code moves on to the Read.  When in separate chassis, you have an asynchronous operation as the Read is happening at the same time as the Write.