Read DMA FIFO from cRIO-FPGA on Windows-PC

[sigmakappa]

Hi Everyone,

I'm working with a cRIO-9076 (Integrated RT-Controller and FPGA) which is connected to a Windows-PC over Ethernet. The primary goal is to acquire analog signals (20 channels at 25 kHz) on the FPGA and stream the data to the disk on the PC. On the FPGA VI the signals are acquired and written into a DMA FIFO which is read by the RT-Controller (RT VI). Then the data is sent to the Windows-PC via TCP. I think this is somehow a standard approach which can be found in many examples etc.

Recently I've noticed that it is possible to open a reference to the FPGA on the PC and to read the DMA FIFO there directly (without using the RT VI and TCP etc. explicitly). Since no other operations execute on the RT VI than reading the DMA FIFO and sending the DATA to the TCP loop (via an RT FIFO) it would be easier if I could read the DMA FIFO on the PC directly and omit the RT VI completely. I did not find a lot of documentation about this topic so I am not sure which is the recommended way. (I guess this is a somewhat unusual case since the cRIO/FPGA is used like a data acquisition card which is connected to the PC and no real-time stuff is involved.)

Are there any relevant differences regarding performance/reliability or are the two methods comparable with regard to this use case? The only requirement is that all samples are acquired and transferred correctly to the PC.

Thanks for any feedback!

Sigma

[crossrulz]

Based on your description, I'm wondering why you even use a cRIO.  Why not just use a cDAQ?

[speleato]

Hey Sigma,

The semantics of FIFO Read are the same, regardless of if it's over the network or local, so you can count on correctly getting all the samples in both cases.

I think your case is going to be borderline for performance though. The network implemenation is not optimized for streaming performance, so if you decide to go this way, I'd caution you to test carefully and also to think about what the future needs of this application may be.

Sebastian

[sigmakappa]

Hi crossrulz,

Thank you for your response. It's indeed not a typical application for a cRIO. Unfortunately I was not involved in the project when the hardware was purchased so I have to live with it for now. What I did not mention in the description above is that there is a IRIG-B timecode generator running on the FPGA which outputs a signal in order to synchronize the data acquisition with an external telemetry system. For this task the FPGA is quite useful (I guess there aren't many DAQ cards that support IRIG timecode natively). But depending on the future progress of the project a hardware replacement could be an option.

Best regards

Sigma

[sigmakappa]

Hi Sebastian,

Thank you for your post. Good to hear that there are no fundamental differences between reading the FIFO locally or remotely. I will test everything carefully and if it's really a borderline case than I have to find another way. Streaming to the cRIO disk or to a memory stick could be such a solution but I want to avoid this if possible since it's not as practical as streaming to the PC directly (e.g. for further processing and transferring etc.). Replacing the hardware could be another option of course.

Best regards

Sigma