08-09-2011 04:01 PM
There is possibility of executing SCTL on FPGA with derived clock rates like 80Mhz. But I found no detail information about the limitations and precision of FPGA in such resolutions, does anybody have an experience on this?
08-09-2011 04:08 PM
The derived clocks are analyzed for timing consistency just like any other clock in the chip so the implemented designs will be safe. Once you start using the higher clock rates, you'll need to apply the various techniques available online to pipeline your data paths and such to actually meet the timing constraints. If I didn't answer your question, we might need a bit more information about what exactly you're looking for.
08-09-2011 04:42 PM
Thanks, this comes to my mind because I read (http://digital.ni.com/public.nsf/allkb/722A9451AE4E23A586257212007DC5FD) that more function limits enforced by derived high speeds.
But what I am looking for is quite straight digital data acquisition with resolution of 80Mhz (12.5 ns), and for this I am planning to use a PCI-7813r. So Iwas wondering if this could really works and gives the accurate resolution?
08-10-2011 08:23 AM
What do you mean by timing resolution?
If you create a derived clock at 80 MHz, and do all your design in that clock domain, you either WILL or WON'T successfully compile the design when it goes through the xilinx toolchain. The limiting factor on this is how much work is being done on each iteration of the SCTL. If you put a wildly complex algorithm in an SCTL and expect it to run at 80MHz, it won't do that (see previous post about pipelining a complex design within an SCTL). However, if a design compiles at 80MHz, it will ALWAYS run at 80MHz, and will always provide you sampling at 80MHz, as long as your inputs are in that 80MHz domain. One of the primary draws of FPGA design is that it is deterministic. If 80MHz is sufficient resolution for your application, you design an FPGA that compiles at 80MHz, then you should have high confidence that your application will work.
Please clarify if I'm not answering the right question.