SIT timing

[Bladhart]

Hello all,

I am using the SIT toolkit. My host VI is on my desktop computer, and I download the model to a PXI-8101 where there is an FPGA card.

Most of the time, the model runs fine. However, sometimes I get what seems like a delay. I need my model to give me an output every 10ms which must get sent through the FPGA card every 10ms. How do I know if:

1) I have set up my model to be running every 10ms

2) My Base_Rate Loop.vi is actually finishing its looping in 10ms or less, and it is not over-running

Thanks.

[Samuel_S · Accepted solution]

Bladhart-

You need to benchmark your code in LabVIEW Real-Time  to see how long it is actually taking:

https://www.ni.com/docs/en-US/bundle/labview-real-time-module/page/get-the-benchmarking-right-real-t...

A really good example is in the LabVIEW example finder > toolkits and modules > Real-Time > benchmarking

I hope this gets you going 🙂