07-04-2006 05:58 AM
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Fixing Invalid MappingsBasically, if you mark the signals you want to view as Test Points then they should be available when running the model on your Real-Time target.
Mappings typically become invalid if the Simulation Interface Toolkit cannot communicate with a model parameter or signal correctly. Additionally, certain simulation options you set in the Simulink application software can cause mappings to become invalid. The following sections provide information about fixing invalid mappings.
Models Using Signal Storage Reuse, Block Reduction Optimization, or Virtual Blocks
Mappings might appear invalid if the model uses either Signal Storage Reuse or Block Reduction Optimization. These items are options you can set in the Simulink application software to reduce the memory footprint of the model. Disabling these options for the entire model makes all signals available for probing but increases the memory footprint of the model. You can mark individual signals as test points to maintain a reduced memory footprint while keeping certain signals available for probing. To make this change, load the model in the Simulink application software and perform the following actions:
For The MathWorks, Inc. MATLAB® application software release 13, right-click a signal and select Signal properties from the shortcut menu. Place a checkmark in the SimulinkGlobal(Test Point) checkbox and click the OK button to save changes.
For the MATLAB® application software release 14, right-click a signal and select Signal properties from the shortcut menu. Click the Logging and accessibility tab, place a checkmark in the Test point checkbox, and click the OK button to save changes.
Note If you previously converted this model to a model DLL, you must convert the model to a model DLL again after marking signals as test points.
Similarly, you might not be able to probe signals from Virtual Blocks such as Mux, Demux, Bus Selector, and so on. Marking signals from these blocks as test points makes the signals available for probing.
Refer to the Simulink documentation for information about Signal Storage Reuse, Block Reduction Optimization, Virtual Blocks, and test points.
07-06-2006 12:49 PM
Hallo Andrew,
thanks for your assistance. I partly solved the problem. to the representation of numeric ones, now must I indicate only for signal graph care.
thanks.
much fun for WoldCup final
07-06-2006 01:52 PM
07-06-2006 07:39 PM
07-13-2006 06:24 AM
hello,
thanks first for your assistance.
The simulation runs, but I have question, I want to replace the controller block in the Simulink model with reaal material controller hardware, to read or write but leisure I signals over Fpga and cRio, so that I the model simulate can-know you conception or experience can realize like one that
Thanks
E.faiz