SPI Example for sbRIO 9606

[ShotSimon]

I'm new to the sbRIO and trying to retarget the SPI Single Port Example for a sbRIO 9606.  I am running into the following errors during the compile see attachment .  I also ended up adding a lvFPgaScratchPad temporary register which I'm not quite sure how it became an option but it did allow me to compile to the errors shown.

I have the following I/O that should be connected in my design CLK = DIO15, CS = DIO13, and MOSI = DIO14 all outputs.

This is a SPI based variable resistor that is connected on the Mezzanine connector that I am able to read when and if it changes.

Any recommendations would be appreciated.

Thanks,

-SS

[Josh_B1]

Hi ShotSimon,

I have been looking into this issue and found a Discussion Forum with a similar issue. 

https://forums.ni.com/t5/Real-Time-Measurement-and/FPGA-I-O-single-cycle-timed-loop-problems/m-p/107...

It appears that the solution was to move all I/O operations inside of the single-cycle timed loops. Could you try implementing this and let me know how it goes.

Regards,

Josh B

[ShotSimon]

Josh B.,

Yes moving the I/O inside allows the code to compile.  Do you know what the scratch register is created for?

Thanks,

-SS

[Josh_B1]

Hi,

I do not know what that register is being created for in your code. These registers are often used for creating look up tables or other applications where memory speed is important.

Let me know if this is useful.

Regards,

Josh Brown