Hello,
I am attempting to use a PXIe system to digitize data, implement a threshold counter via an FPGA, and stream data to disk at a lower rate than the sampling. My system uses the following hardware:
Digitizer: NI 5781
FPGA: PXIe 7965R
Hard Disk: HDD 8263
The NI 5781 has a sampling rate of 100MS/s and I am hoping to buffer data to disk at a rate of 1 MHz to both decrease file size and speed up the analysis performed on the files. My initial idea was to have two SCTL, one clocked at the 100MS/s (using the IO Module Data Clock 0) which retrieves the data and implements the threshold counter, and another operating at 1MHz (derived clock) which sends the current count to disk (via a target to host FIFO).
First, I noticed that from the 40MHz onboard clock it will be better to derive a 2.5 MHz clock (1/16), which is not a big deal. Initially, I was trying to use a target-scoped FIFO to send the data between the two SCTL but I am having compilation errors related to the clocks.
Before getting too deep into my approach, is this a good way to tackle my problem? Also, instead of a target-scoped FIFO maybe it would be better to use a global variable? Is there any way to sample at a lower rate intially?
I had some success using case structures and only sending the data to disk only when the loop counter was equal to some value (say 100 to get a 1MHz buffer rate), and then resetting the loop counter. This felt like a hack and I thought having two clocks might be more elegant. I have attempted searching online for guidelines but haven't found anything too useful. Any help would be greatly appreciated!
Best
Nolan
