Synchronizing clocks on NI-5785

[erikw3]

I have a PXIe-5785 IO module in a PXIe-1082 chassis. The FPGA target in my labview project has an 80MHz top level clock and the IO-socket has a 200MHz data clock.

I have two single cycle timed loops running in parallel:
Loop 1 is running on a 100MHz clock derived from the 80MHz top level clock.
Loop 2 is running on the 200MHz data clock (it has to use the data clock to be able to generate analog output).

It appears that loop 2 is running a little more than twice every time loop 1 runs. This causes problems as loop 1 is producing data and loop 2 is consuming it, so after a while loop 2 will have no data to process for a cycle.

How can I synchronize my loops so that they do not have this clock drift? I suppose they should run with clocks derived from the same base?

I have found some documentation about clock selection for similar adapter modules (like this: http://www.ni.com/documentation/en/transceiver-adapter-module-for-flexrio/latest/ni-5782/5782-single...) that has 'user command' that can be used to change 'User Data Clock Settings'. For the 5785 I can't find anything similar.

[Terry_ALE]

Every value that comes into the fast loop could be held in a shift register so it can be written twice to the analog output.

After it is written twice then you can get a new value from the FIFO read.

[erikw3]

Thank you, that is a workaround that I will try if there is no real solution. Repeating a sample every now and then will of course distort the signal slightly.

But surely there has to be away to synchronize the clocks? There are a number of clocks available, for example a 100MHz clock on the backplane of the chassis. And there are synchronization options for other adapter modules, but I can't find anything on how to do it for the 5785..

[Intaris]

You will need a common base clock in order to prevent phase drift.

Two distinct (unrelated clocks) cannot be synchronised in this way.  You may be able to compensate for the difference, but the clocks will remain distinct.

Why don't you create a derived clock from the 200MHz clock instead of the 80MHz onboard clock?

[erikw3]

That is exactly what I want to do. Derive all clocks I need from the 200Mhz data clock . Labview won't let me do it. I can't find any way to create a derived clock from the data clock on the adapter module. With the FPGA base clock, it is simply right clicking on the clock and selected 'create derived clock'. The data clock on the adapter module have no right click menu at all.

[Terry_ALE]

How is data being sent from the 100 MHz loop to the 200 MHz loop?

Do they need to be separate loops?

[erikw3]

Data is sent using a FIFO

Unfortunately they have to be in separate loops. The application does a lot of processing on the data that is not able to run in the 200MHz clock, most of the processing is done in 10MHz single cycle timed loops. With a 20 times faster clock, the FPGA would (probably) not be able to keep up. The last loop needs to run on the data clock of the IO module, as that is the only clock that allows the program to actually generate output on the analog output channels.

[Terry_ALE]

Understandable (re multiple loops and rates).

If the source is always going to be 100 MHz, then somewhere you need to resample (interpolate).  Above I suggested this and you said that you do not want to distort the signal.  I am not sure how else you can make 100 Mhz into 200 Mhz.

This does not seem to be a phase issue.  Trying to make clocks synchronized when you have data being shared by a FIFO will not solve the problem of a starved FIFO.

[erikw3]

The number of cycles per sample or interpolation is not the issue. Never mind the data.

I need the second loop to execute exactly twice for every time the first loop executes. If the second loop was timed by a clock that was derived from the clock that timed the first loop, this would be the case.

In an earlier project, we used a different adapter module, the 5782. It had an interface for using an external clock as data clock in various ways. There where a bunch of different settings and an interface in labview for modifying those settings. This way they adapter IO module shared a base clock with the rest of the FPGA that all clocks were derived from.

With the 5785 I expected to be able to do something similar, but I can't find anything in labview, no examples, no documentation about external/internal/reference clocks

[Terry_ALE]

What is the method to determine that the two loops are off by more than a factor of 2?