Synchronizing clocks on NI-5785

[erikw3]

Loop 1 puts some test signal into the FIFO (once every 10 cycles)

Loop 2 reads the number of samples available in the FIFO every cycle. Once the number of samples in the FIFO reach a certain threshold (=64), Loop 2 start fetching samples every 20 cycles. Over time, the number of samples in the FIFO decreases (I can see this as the number of samples in the FIFO is written to the host periodically)

[Terry_ALE]

How does the output look on a scope?  Do you see a drift there?

[erikw3]

Yes, I can see the drift on a scope as well, that was how we discovered it in the first place.

I think I found a solution, however:
There is a setting in the property page on the IO module called 'IO sync clock'. I set it to enabled, and selected the PXI_CLK100 option. Then I changed all SCTL in my program to use either 'data clock' or a clock derived from the PXIe_Clk100 clock that was available in the project. The clock drift appear to have vanished!