Hello,
I'm trying to use the Synchrophasor VI in Labview FPGA but there's something about it I don't understand and since it looks to me to be partially encrypted, I was wondering if you can give me some explaination. In particular:
1)Why in the "resample VI" there is the need to specify the number samples per cycle and what does it change if I change this number?
2)Why do I need to set the nominal frequency of the signal if then the frequency of the signal is computed again?How this value affect the computations?
It looks to me that everything is set in order to make the input signal suited for this subVI(Phasor->LP 1.2-12). Why??
