Transferring data from hostvi to fpga

[nowoxi]

Hi,

I need advice I want to transfer a dynamic array whose elenent can change during transfer from a host vi to an fpga. I would appreciate I could get advice with the best method of transfer, should i use DMA FIFO, circular buffer or anohter method of transfer. At the moment I the fpga vi just get the data from a control.

[NapDynamite]

Use DMA FIFO for better data acquisition. 

http://www.ni.com/white-paper/4534/en/

Regards.

[nowoxi]

thank you for your response. Is there an example that writes to FPGA from host or is it ok to just do the opposite of what is in the link you shared.

[NapDynamite]

Using DMA FIFO is the best way to interface data from FPGA to RT processor (Host). Just go through the link I have posted and also search for examples for the particular embedded platform you are using (cRIO OR sbRIO).

[nowoxi]

Thank you very much. I actually have been able to control the flow. I guess I haven't configured the timeouts properly.

I am sending and array from the host to the fpga i have both host and fpga fifos in a while loop. Might this be the reason the array is read multiple times

[nowoxi]

I would appreicate so help with how the data flow is handle by matlab. I have been thinking of how i could test it but havent figured it out. I am sending an array to the fpga from the host. A simple application is showing me that the data is been sent but i dont know when exactly it is recieved by the fpga I cant use it in the fpga. I know its taking the array in parralel and then passing it to the fpga serially but i dont know what controls the output serially is it clock cycles or is it time cycles?