Two data types transferred via DMA FIFO: Hexadecimal and FXP - incorrect decoding at Host side.

[Tom_wolf]

Hello Guys,  

I'm begining my adventure with LabView.

I need to transfer two types of data from FPGA_main.vi  to Host_main.vi via DMA FIFO.

One channel type is hex type ( decoded message from sensor with SENT Interface)

Second channel is FXP data type from AI ( NI 9222 C series module).

My idea was to convert Hexadecimal data type from HEX to FXP because FXP is also from AI.

In the next step I Build Array and push Array to DMA FIFO

FPGA_MAIN

RT_Main

Hexadecimal String received on Host side is OK.

The problem is data transferred from AI: on the FPGA I have something like -0.0007123...  and received at Host is 2159983372.

What I do wrong?

I appreciate Your support

[Intaris]

You have a coercion dot on the Data in for your DMA meaning there's a datatype mismatch between your DMA and the data you're sending.

What's the datatype of your DMA?

And what is the FXP type you are sending?

I see your DMA is U32, so if your bits are OK, then you need to re-interpret the bits as the correct datatype.

Also, HEX isn't a datatype, it's a display method. FXP and U32 are datatypes.

[raphschru · Accepted solution]

Since you want to transmit a mix of binary data (SENT) and numeric data (MOD6/AI0), choosing a U32 FIFO seems to be a good idea because all data types can easily be converted to and from U32. However that means that you must find a way to convert your fixed point values without losing data (by unwanted rounding or overflow).

There are functions "Fixed-Point to Integer Cast" and "Integer to Fixed-Point Cast" that allows you to do that without data loss.

FPGA:

Host:

As a side note, I suspect your data "corruption" happens here:

Regards,

Raphaël.

[Tom_wolf · Accepted solution]

Hi Raphaël.

Let me apologize for delayed feedback - I had some other issues.

Proposed solution: implemented, tested - It works.

Thank You.

Another questions:

 - scaling AI to engineering units ( from Volts to Newtons) is better to perform at FPGA or Host side? I have NI 9222 Analog Input module.

 -  My FIFO stops value streaming after 1024 samples as setup-ed in FIFO Properties.

What Can I do to contnous data transfer from FPGA to HOST?

Thank You 

best regards

Tomasz

[Tom_wolf · Accepted solution]

Hi

You had right. My DMA FIFO datatype was incorect.

I setup as You recommend and now works OK

Thank You for looking to my problem

Best regards

Tomasz

[raphschru · Accepted solution]

---

@Tom_wolf wrote:

 - scaling AI to engineering units ( from Volts to Newtons) is better to perform at FPGA or Host side? I have NI 9222 Analog Input module.

---

From my own experience, scaling is usually done on the Host side. This takes less FPGA space (no additional operation, no additional control for scaling factors and offsets), and sometimes you need the raw (not scaled) value on the Host side anyway. You could argue that the FPGA is faster and could do the scaling effortlessly, but in my opinion, it would require to scale a massive amount of data to see a real difference in performance.

---

@Tom_wolf wrote:

 -  My FIFO stops value streaming after 1024 samples as setup-ed in FIFO Properties.

What Can I do to contnous data transfer from FPGA to HOST?

---

You need a task on the Host side that continuously reads elements from the FIFO. It must be fast enough to avoid filling up the FIFO buffers. You can also configure the buffer size on the Host side to allow you to read from the FIFO at a reasonable frequency. Open the Example Finder and see examples "Streaming Data (DMA)" or "Interleaving Channel Data (DMA)"...

Also notice that a DMA FIFO always has 2 buffers, see my answer from a previous post for more explanation:

https://forums.ni.com/t5/LabVIEW/Labview-FPGA-DMA-FIFO-number-of-elements-to-read-does-not-match/m-p...

[Tom_wolf]

Hello Guys,

I'm struggling with correct data receiving at HOST side.

My device is cRIO 9068. On the FPGA side I have simple data pushing to the DMA FIFO:

There is 1-D Array of U32:

•   Index #0 - Analog data 
•   Index #1 - Digital data

On the Host side I'm trying:

• to get all data from DMA FIFO and push it into Queue - this a producer Loop
• receive all data from Queue - this is consumer Loop.

Data received in consumer loop have missing messages;

Below is producer Loop;

and consumer Loop:

How can I optimize data transfer between FPGA and Host?

How can I optimize data transfer between DMA FIFO and Queue? - I suppose that data pushing from DMA FIFO to Queue is somewhere not syncronized.

I used also architecture with 2 x Invoke Method for checking Elements Remaining but still data is lost.

Could You support me?

[raphschru]

Hello Tomasz,

The way you are reading from your DMA FIFO seems quite inefficient. You only read 2 elements every 10ms (when "Dequeue Element" times out). I don't know at which rate you receive SENT data, but that may be faster than 100Hz.

Also, setting a giant buffer (+10M elements) to the DMA FIFO only delays the moment when it fills up completely. Then you start losing elements because the "Write FIFO" on the FPGA side cannot write elements anymore.

A good practice on the host side is to read the number of available elements first, then read the biggest chunk of data possible, and decode multiple samples at once. Here is a simplified version of your host VI:

Here I read the biggest multiple of 2 elements, then process the whole chunk of data at once, which is way more efficient than processing each sample one by one (even further in the process for saving your data to file).

Also, DMA FIFO buffer on the host side should be reasonably sized according to the data rate coming from the FPGA and to the rate at which you read elements on the host side, plus some margin. Example: If your SENT device produces values at 5kHz and you read elements at 50Hz on the host side, your FIFO buffer must have at least packet_write_rate / read_rate * packet_size = 5000 / 50 * 2 = 200 elements. Then you can add a margin in case reading loop has a little bit of jitter (period may not be deterministic). Example: 1000 elements on the host side should be sufficient in your case. Regarding the buffer on the FPGA side, I usually let the default one (e.g. 1023 elements) unless I need to save some FPGA space.

PS : When attaching FPGA VIs, it is better to attach a complete project (containing both the host and FPGA targets) because otherwise we are missing objects defined at project level such as FIFOs, Memories, Registers, Handshakes, IOs... Also it includes all subVIs. You can create a minimal sample project if you don't want to share all your source code.

PS (2) : This time you could have created a new thread, because this is a different problem that calls for a different answer. The original issue was about data types casting, now it is more about loop timing/synchronization.

Regards,

Raphaël.

[Tom_wolf]

Hi Raphaël.

Thank You very much - now I have really good progress - Don't missing frames reported.

Ad.PS(2) - You have right - that is new thread.

Ad. PS - Attached are files from project project with all files.

I didn't measure data rate but is fast ( cRIO 9068 /40 MHz).

Because I have LV 2020 -32 bits I was not able to open attached VI. I implemented Your code with some changes and now I have no missing data.

I decided to eliminate Queue and analyze data in the first consumer Loop.

I have observation that Express VI streams data to TDMS file with time stamp 1s 

Below screenshoot from excel and attached TDMS file.

How can I  improve this?

best regards

Tomasz

[raphschru]

Extend these "Build Waveform" nodes, then you can specify the "dt" in seconds:

By default it is set to 1s, but you can set your actual data sampling period.

PS (3): When attaching more than 3 files, wrap them in a zip (standard .zip, not .7zip, not .rar). Do not forget the .lvproj file.

Regards,

Raphaël.