Two different loop timing and each execution in FPGA

[catalysthw]

Hi, LV experts!

 I wondered that two different loops in FPGA are possible to be implemented with each loop speed.

Ex)   SCTL and While Loop in a same FPGA VI

 SCTL = 1 tick    vs    while loop 43 ticks (loop execution)

Also,  Is it possible to transfer T/F signal from SCTL to while loop in a same FPGA VI via a local variable even though they have different loop execution speeds as above?

[crossrulz · Accepted solution]

Yes you can.  Instead of asking, you could have just tried it.  It would have been a lot faster for you.