USB 8451 I2C acknowledge bit problem

[Mr.F]

Hi Gary,

For troubleshooting purposes can you recreate a program in a single script that runs once? Also, can you try using the simple I2C commands (as opposed to the “advanced” palette) in lieu of the script?

[ggaryt]

I'll give it a shot Matt and pass what I come up with along to you.

Gary Tyrna

[ggaryt]

Good Morning Matt,

I have created a single write function but as I have tried this method of communicating with the Xilinx eval board earlier in this project and I'm getting the same results.  The problem is that function runs but there is no activity on either the SDA or SCL line so nothing is written.  So I'm not sure what is missing, I took this write function from the I2C basic write example.  I have attached the VI and the SPY capture for your review.

Gary

[Mr.F]

Hi Gary,

What do you mean by no activity on the SDA or SCL lines? Do you not see the same behavior on the scope as you did last time? What value are you passing the Xilinx board for the address and clock rate? What values do you have in the Array to write? This gets the same “No ACK” error message, right? What are you using to program the Xilinx chip?

[ggaryt]

Hello Matt,

What I mean is there is nothing, the SDA line stays high and nothing ever starts. 

The address is 8h and the clock rate is 100KHz and I'm writing a value of 3h. 

There is no error since there is no start down clock. 

We are using the Xilinx program that came with the development board.

Gary Tyrna

Tahoe RF Semiconductor, Inc.

[ggaryt]

Matt,

On the programming of the Xilinx FPGA it is through a USB interface pod to the eval board JTAG port.

Gary

[Mr.F]

Hi Gary,

Can you double check the address and values that you’re writing? “8h” and “3h” are not valid Hex values. To be clearer I was asking about how the Xilinx board is set up to communicate via I2C. Did you program the FPGA code yourself? Do you have access to a slave I2C device for testing purposes?

[ggaryt]

Matt,

The address is a 08 Hex there are only 16 registers total in the design, registers 0-7 are for internal usage only and the last eight ate control and status registers.  The data is just a hex 3 because it is data other than zero but since I'm not getting the acknowledge back there is never data written to or read back from the Xilinx board.  The Xilinx evaluation board is loaded with code development by my boss Andy Probst.  The scope signals I had sent to you earlier are from that code along with the acknowledge bits on channels 3 & 4.  I have the Xilinx evaluation board here and using the NI-8451 pod as the master interface.

Gary Tyrna

Tahoe RF Semiconductor, Inc.

[ggaryt]

Hi Matt,

I was able to get the single write to work and it returned the same error message as did my previous write function.  I have attached the error message and the SPY capture for your review.  As you'll noticed that the acknowledge bit (ch3) generated by our I2C interface program on the Xilinx board is there but the SDA line doesn't seem to be going tri-state to allow the ack bit through.

Gary Tyrna

Tahoe RF Semiconductor, Inc.

[Mr.F]

Hi Gary,

What did you do differently in order to get the single write to work? Also, since the SCl and SDA lines are open drain, nothing should impede your FPGA’s ability to drive the SDA line to ground in order to ACK appropriately.  Did you connect the 8451’s ground to the FPGA’s ground?  If they are referencing different ground plains, the FPGA might not be able to fully pull down the SDA line.