Hello Matt,
My boss Andy and I went through all the e-mail I have been corresponding with you through this problem and he came up with an idea of looping the input data from the Xilinx internal register back out to another pin on the connector to see what the Xilinx was seeing. Well when he finished the modification to the code and I loaded it into the Xilinx part the next write I did the Xilinx was able to returned the acknowledge bit and I'm up and running.
As to what changes he did in his code in order to reroute that internal SDA input line to loop back out caused something in the fpga to change which is allowing the acknowledge bit through.
I don't really believe that I can put up a solution to the problem I was having. It seem to be something with the Xilinx Virtex-5 and/or the code but I don't have access to what was changed so I'm just going with it is working and I'm able to obtain write and read acknowledges.
Thanks you for all you help and if I can get some information from Andy as to what changed to allow the acknowledge bit through I'll pass that along to this posting.
Take Care and let me know if you have any other questions, I'll do my best to answer them for you.
Gary Tyrna
Tahoe RF Semiconductor, Inc.
