Understanding the digital output functioning of NI-9402

[okidoki21]

Hi,

I have a very basic question where I am trying to understand the functioning of the NI-9402 digital output using LabVIEW. I have connected the 4 digital outputs of NI-9402 to 4 analog inputs of NI-9239 such that Channel '0' of 9402 is connected to Channel '0' of 9239, and so on till Channel '3'.

I have designed the 2 separate set of projects:

1. Turning digital channels on NI-9402 ON and OFF in RT-Scan interface and reading digital output signals using NI-9239 in RT-Scan Interface.
2. Turning digital channels on NI-9402 ON and OFF in FPGA interface and reading digital output signals using NI-9239 in RT-Scan Interface.

I cannot understand why these ways show different behaviors.

1. In RT-Scan interface, 9239 shows digital low values in the first cycle (Cycle no. 0) and shows digital high value in the 2nd cycle (Cycle no.: 1).
2. In the FPGA interface, 9239 shows digital low values in the first 2 cycles (Cycle no. 0 and 1) and shows digital high value in the 3rd cycle (Cycle no.: 2).

I do not understand why the program behaves differently. Does this behavior also depends on the loop time? Currently, it is set to 5 secs.

Kind Regards,

Okidoki

[ZYOng]

It takes some time for the module to get ready for output. You can refer to the shipping example <LabVIEW>\examples\CompactRIO\Module Specific\NI 9402\NI 9402 Digital Line Output\NI 9402 Digital Line Output (FPGA).vi

and monitor the ready before writing value.

[okidoki21]

Hi ZYong,

Thank you for your reply!

I am not configuring the channels in the FPGA code as shown in this example. Do you think that it is the same case for my code? Also, does it take 1 iteration to initialize and then execute in the next iteration? It seems like the digital output in my case becomes high every time in the next iteration than the one in which they are commanded to be so.

Kind Regards,

Okidoki

[JÞB]

POINT1 It sounds like your read is happening before your write. Alternatively the DO propagation delay is greater than the vis Write - Read timing. Refer to the hardware specs for the 9402 which state the propagation delay as <65nSec with a 18nSec typical but there are 2 footnotes 🤔 so watch out for those too.

POINT2 All of that assumes that tha Tasks themselves are running before iteration 0!  DAQmx does need a finite amount of time to verify, reserve, Commit, and start any Task.  

In other words,  I would expect to see some explainable timing inconsistencies between iteration 0 and 1-n.  If you have addressed POINT1 we can ask if you must address POINT2, using other techniques such as DAQmx Control Task.vi, or if iteration 0 can be ignored.