Use of memory block in different clock domains (or some advice to use another approach)

[saccon]

My mistake!

Because PXI_Trig0 is driven by another board - which was not initialized at my test VI - I am assuming the trigger had an unpredicted state - sometimes being read as True/False and triggering the acquisition. The problem was solved running the 7851R FPGA code, which controls the mentioned trigger. Thanks again.

[saccon]

Hi,
The triggering is working fine. Apparently, the required data is being acquired and written to the DRAM FIFO using a SCTL. Another loop is used to read it from the memory for further processing, like it was described in the beginning of this topic. However, not all data are 'reaching' the second loop. For example, if 4000 points are written to the FIFO, the second loop reads only 80. The boolean 'data available' is false - no more data is available. The SCTL is running at 100 MHz (ideally it will be 200 MHz), while the second loop runs at the Top-Level clock, which is 80 MHz. I attached an example project. I appreciate if somebody can help me with this. Thanks.

=S

[saccon]

Hi all,

No progress since last time. I attached the project file and put some pics of the FPGA code and the host front panel. The problem still is related to the DRAM memory. Apparently I can write all acquired data using the Write node, but at the Read loop only few points are recovered.

To overcome the memory latency (or its non-deterministic behaviour), I am using a built-in FIFO to buffer the data. According to the counters, all data acquired at the first SCTL is recovered on the second loop (where the FIFO transfer data to DRAM memory), but only a small fraction arises at the third one - where data is read from memory for processing -, a while loop. At this time I could not determine if the problem is at the 'write to memory' SCTL or at the while loop. They work at different clock domains: While the SCTL runs at 100 MHz, the top-clock is running at 80 MHz. I tried to change this speed, but it did not change the behaviour. I hope I could explain it clearly.

I appreciate any help.

Thanks,

Fernando