Using Flat Sequence Structure in FPGA

[tpendleton18]

Hello,

I have written a simple FPGA VI to write and read cRIO data. Right now, I have a while loop with a loop timer to control the sampling rate of the data. In many FPGA examples, I have seen people use flat sequence structures inside of while loops to perform data collection. What is the main difference between that and what I am doing? I am processing the data at around 1000 hz, so it is quite easy for the FPGA given its high speed. Also, within this code I would like to process the data before sending it to the FIFO and RT VI. All the calculations done are in the RT VI shown in the picture. Again, would the flat sequence structure be more beneficial or should I stay with the while loop? Pictures provided below.

[GerdW]

Hi tpendleton,

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@tpendleton18 wrote:

Right now, I have a while loop with a loop timer to control the sampling rate of the data. In many FPGA examples, I have seen people use flat sequence structures inside of while loops to perform data collection. What is the main difference between that and what I am doing?

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The difference is: others use a flat sequence, you don't use them…

Flat sequences are recommended to ensure proper timing: have the wait in the first frame, then the IO nodes in the second frame. Doing such stuff in parallel in your FPGA fabric might be less "strictly defined"…

• Why do you use ReplaceArraySubset in your FPGA VI when you could use a simple BuildArray node with 4 inputs?
• I would use two loops to separate AI and AO nodes…
• Why do you attach two files with same name, but different content?
• Why do you attach a scaled down version of your RT block diagram image?
• Why do you use the same ReplaceArraySubset approach here instead of a simple BuildArray?
• Why don't you place those calculation/scaling stuff (after reading the FIFO_to_RT and before WriteDelimitedFile) into a subVI to clean up your code?
• Why do you need a Wait(ms) and a GetTickCount in the same loop? Wait(ms) provides the very same output value as GetTickCount!

[tpendleton18]

So the answer to my question is it doesn't matter? You provided multiple answers to questions I didn't ask. Please keep on topic instead of changing subjects.  Also you talk about not running loops in parallel as to keep my VI "strictly defined" then contradict yourself by saying I should run parallel loops for input and output.

[GerdW]

Hi tpendleton,

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@tpendleton18 wrote:

So the answer to my question is it doesn't matter?

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No, I didn't say so.

I gave a recommendation and an explanation for that recommendation...

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@tpendleton18 wrote:

You provided multiple answers to questions I didn't ask. Please keep on topic instead of changing subjects.

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I give comments on your code, expressed as question because you should have a reason to implement your code as it is. Take those comments or don't...

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@tpendleton18 wrote:

Also you talk about not running loops in parallel as to keep my VI "strictly defined" then contradict yourself by saying I should run parallel loops for input and output.

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Where did I wrote about "not running loops in parallel"?

Right now the AI and AO in your FPGA loop run without any defined execution order (because of THINK DATAFLOW): separating them into two loops will not make any difference in this aspect. IMHO it gives cleaner code when you run multiple loops on your FPGA, one loop for one task...

[Terry_ALE]

Sequence structures are to force an order of things.  You can force an order with wires.  Some people like sequence structures from a visual standpoint.