Where does the FPGA DMA FIFO locate?

[ErZim]

Hello, I need the information about DMA on sbRIO board.

We use sbRIO 9606 and the board can communicate with host PC and FPGA target via DMA.

Just my colleague is curious that where the DMA's memory locates. Does the memory locate on FPGA chip?

I mean, the Xilinx chip has memory area (FIFO area) for DMA transfer?　Or peripheral circuit is existed?

From the knowledgebase; http://digital.ni.com/public.nsf/allkb/0A008919E1551B1A86257B9D00764FC4

sbRIO has 5 DMA channels.

The LV help has a diagram but it does not answer my colleague's question.

http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpgaconcepts/fpga_dma_how_it_works/

I checked Xilinx website also, but I couldn't reach the answer.

sparten-6 LX FPGA has 5 memory interface controller blocks and I am guessing that are DMA transfer memory. Is it correct?

Even though, I can not reach the answer for physical location on FPGA board. The top diagram on page 4 of the following looks good but not answer for my question;

http://xilinx.com/publications/prod_mktg/Spartan6_Product_Brief.pdf

We look forward to get the reply for this issue.

Regards,

[Sam_Sharp]

I think the sbRIO uses the Xilinx Zync chip - the RT microprocessor and the FPGA are located on the same physical chip - so the DMA is located on-chip.

If you do a google image search for 'xilinx zynq' - there are a few block diagrams that show the architecture.

Edit: Apologies, I thought you were referring to the newer System on Module (SoM), which is a Zynq chip. I think the older Spartan boards use off-chip memory?

[Dragis]

As mentioned in the DMA concept document you mentioned, there are two buffers for each DMA channel. The first is accessible from the host which is located in the targets DRAM. The other is on the FPGA and is generally implemented in the block memory of the FPGA logic because it must support being read and written every clock cycle. 

[ErZim]

Dragis, thank you for your message.

"The other is on the FPGA and is generally implemented in the block memory of the FPGA logic because it must support being read and written every clock cycle. " is helpful and now I am clear the block memory and DRAM section at the following;

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_storing_data/

[ErZim]

Sam_Sharp, thank you for your message.

It seems 9606 is not that one, but that's my first time to check the XIlinx Zync chip and I'm glad to know it.