While Loop inside a Case Structure executes only Once in FPGA Target

[mini09]

I`ve an NI cRIO 9012 RIO card for the HIL System. I`ve an FPGA Target file where I use a While Loop and inside a while loop I use Case Structure to check for true condition inside that i`ve the function of enabling the ports and selecting the analog and digital ports. But for my code the code is executing only once not on repeted times as we`ve in the LabVIEW Environment.

I also need help in optimizing the code. I`ve seen people using Timed While Loop in FPGA Target i`m not using in either case.

I`ve attached my FPGA file with the Version of LV2012.

Awaiting your feedback.

Thanks and Regards,

Ganesha Moorthy

[dan_u · Accepted solution]

You have while loops inside the case structure with a false constant wired to the stop condition. These loops obviously will never stop so your outer while loop (containing the case structure) can never iterate.

This has nothing to do with the FPGA target, the same will happen in the development environment.

[mini09]

Thanks dan_u, Since i`m not sure whate is happening in the target I mentioned FPGA Target. I was sure there was some mistake in the code. Can I make the while loop stop by looking for thechange in the boolean connected. 

My case is I need to turn on the pins only after the battery and ignition is Turned on. So I used while loop with the case structure shall we remove the while loop so that the operation will perform on each iteration on the outer while loop. 

If so will I be able to generate the same signal as I`m doing now?

[dan_u]

I don't understand what you want to achieve. If you only need to execute the code inside the True case of the case structure once then it should be fine the way it is. The outer while loop will iterate (doing nothing) until the conditions become True then it will execute the code in the True case and remain in there.

If you need to execute the code in the True case several times then you need a way to stop your inner while loops.