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array manipulation from fpga to tdms

Hi Labview community,

 

i'm working to optimize my code.

i acquire data from fpga using DMA

i read DMA in real time vi and i need to manipulate it before logging it usind advanced tdms write

data manipulation means that: reducing size of DMA (desampling) but having also option for averaging

 

i need help to understand which is the better way. i used to manipulate like:

Michele___2-1740654041032.png

 

 

I NEED HELP TO:

A) is there a vi similar to Decimate (continous).vi that allow me to pass direct the array interleaved data that come from FPGA without access it to retrive channels? there is something that accept data I32 or I16 instead of DBL (5 picture above)?

B) which is the best way (1, 2 , 3 or 4 picture above) to prepare FPGA array to TDMS advanced write?

C) data to TDMS advanced write could be interleaved or not, it depends by the way i prepare it. which is the better way?

 

in the real application that could be some real order of data:

 

PXI

20/30 channels at 500KHz logged continous

20/30 channels at 100KHz logged continous

100/150 channels at 1 KHz logged continous

 

CRIO

10 channels at 500KHz logged short time

50/100 channels at 1 KHZ logged continous

 

thank you for support

 

Michele

 

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Message 1 of 3
(192 Views)

I do not know which one is faster. Below is an option where all manipulations are in-place. Should save memory but may be slower. Data channels are in columns, so you should be able to use interleaved TDMS data. Lastly, never used the decimate functions, but believe you need to keep double output. Decimate data should low pass filter the data then decimate to prevent aliasing. That low pass filter should introduce non-integer values.

 

snip.png

 

EDIT: Reshape final array for TDMS input 

Message 2 of 3
(164 Views)

I like mcduff's answer.

If you wanted to try to offload the decimation to the FPGA before it even gets to the host/rt, I believe there are a couple implementations floating around. The "Rational Resampler" on the FPGA Math and Analysis palette can support up to 32 channels interleaved (not sure why the limit is 32 channels):

Newton_Petersen_1-1741290909148.png

 

Newton_Petersen_0-1741290785228.png

 

Message 3 of 3
(75 Views)