I want to get 26 U32s from the FPGA on a cRIO-9035 up to my PC at a rate of 200 kHz. The bottleneck appears to be moving information into an RT FIFO, then getting it out again and putting it in an array, to minimize overhead when transferring the array to the PC.
The enclosed VI tests the speed at which information in an RT FIFO can be transferred into an array. In the full application, the array is sent up to a PC via a network stream, and by bundling information into an array, we minimize the streaming overhead. If running correctly, Index Out should always be a multiple of 4000. If the consumer can't keep up with the producer, it misses some information, and Index Out jumps by more than 4000. Using a cRIO-9035, this runs well with a producer period of 20 usec, but at 10 usec, the CPUs are overburdened and the unit loses connection with the PC and must be physically reset.
This is being run on a cRIO-9035, with a dual core Intel Atom chip runnning at 1.33GHz. 10 microseconds allows for 13,000 clock cycles in each CPU. Shouldn't it be able to put 26 4-byte numbers into a FIFO, and take them out of that FIFO to put them into an already-established array, in a lot less than 13,000 clock cycles?
Chris
