cRIO FPGA loops sync problem

[gy10c]

Hi,

I am trying to program the cRIO FPGA. The overall application is like to let the DAC to output a waveform periodically and the same the waveform can be cut off to zero output once the ADC is triggered. To do that I let the DAC and ADC run in different loops in parallel. But it seems problematic to use the local variables as communication method between the two loops. See the picture attached. The code does not work. If I set the awg gate on before run FPGA VI, the waveform output is there, but not what I defined.  If I just run the FPGA VI without setting any controls, there is no waveform output.

Can anyone tell me what is the right method to achieve my application?

Thanks!

[GerdW]

Hi gy,

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@gy10c wrote:

But it seems problematic to use the local variables as communication method between the two loops. See the picture attached. The code does not work.

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Well, there are too many locals visible in this image. And too many sequence frames, even though they have their reasons in FPGA programming…

And what about that classic Rube-Goldberg of comparing a boolean value with TRUE???

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@gy10c wrote:

If I set the awg gate on before run FPGA VI, the waveform output is there, but not what I defined.  If I just run the FPGA VI without setting any controls, there is no waveform output.

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What happens to the IO nodes when there will be an upstream error?

What is the default value of all those controls? Do you initialize them somewhere after starting the FPGA VI?

Are you sure the "awg" loop actually runs as expected when you switch the "AWG gate"?

[gy10c]

Hi, GerdW

Sounds like too many reference to local variables are not good, then what should I use? a FIFO? or register? Should I assume a local variable is fine to use if it is only in one loop and make sure they get read/write not by more than on source?

What is the better way to achieve the function for the "comparing boolean" part?

Thanks! I would like to learn!

In terms of function of this program, I have been tried long time. I have observed the following:

1. if I delete the bottom loop and run the FPGA VI in RT VI as "set awg gate=true" -> Run, the DAC output is right as shown in the oscilloscope. A period waveform.

2. if I delete the bottom loop and just run the FPGA VI, then set the awg gate=true later, there is no DAC output.

3. if I set the default awg gate value to "true", the output waveform seems correct.

Since I can output the waveform correctly, only the awg gate part not work, there should be no upstream error. The default value of all controls are "False". I don't initialize them in the code, but before the FPGA VI runs, I call a "reset" in the RT VI.

[gy10c]

I now understand the Rube-Goldberg issue, my brain just get chaotic when study FPGA.

[gy10c · Accepted solution]

I think I have figured out. Basically the local variables are not good for synchronize between two FPGA loops. They are called lossy way to transfer data in the manual. I am now using the VI defined FIFO which seems to work. See the code attached.