cRIO FPGA mulitple function

[gy10c]

Hi,

I have been using the cRIO for data measurement for some time. So far the cRIO with ADC and DAC have been used as two ways. One is for slow measurement, basically send a voltage to my device and then measure a voltage back. The second function is more complex, use cRIO to trigger a function generator, then use the ADC to measure fast data points. These two function are currently using different RT VIs and FPGA VIs, the PC program simply call them as needed for different purpose.

My question is what is the best way to combine these two functions together? I mean to have a single RT VI between FPGA and the PC, and one or two FPGA VIs to be called. Thanks!

I currently have two solutions in mind:

1. uniform the two functions into a single RT VI and single FPGA VI. Because the two function will involve the cRIO ADC/DAC modules to be set into different modes. The FPGA VI will looks complex. It  really has to contains the two functions, plus code deal with switching between functions, probably with many loop in loops.

2. use a single RT VI, but separate FPGA VIs. This will keep my code easier to read and with less changes. But the RT VI will need to switch between the two FPGA VIs frequently. I am wondering does frequently load and reload the FPGA VIs can shorten the life of the FPGA? Is the "download" of the bitfile only deal with ram or flash rom?

[GerdW]

Hi gy,

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@gy10c wrote:

So far the cRIO with ADC and DAC have been used as two ways.

One is for slow measurement, basically send a voltage to my device and then measure a voltage back.

The second function is more complex, use cRIO to trigger a function generator, then use the ADC to measure fast data points.

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The only difference between both is the number of samples you want to read from your AI channel!

Both options use a function generator (the first method just a simple sine/rectangle one with zero amplitude and an adjustable offset). Both options read data from your AI channel, you only need to change the sample rate or the decimation factor…

So what is the problem to handle both options with just one VI?

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@gy10c wrote:

1. uniform the two functions into a single RT VI and single FPGA VI. Because the two function will involve the cRIO ADC/DAC modules to be set into different modes. The FPGA VI will looks complex. It  really has to contains the two functions, plus code deal with switching between functions, probably with many loop in loops.

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Why do you think you will need to stack loop within loops?

Which "different modes" do you need to handle?

[gy10c]

Hi GerdW,

Thanks! Let me clarify. Also I attached the VIs contain the two FPGA functions.

The first function is as you described, very basic. I just need to send/receive one data point as demanded by the PC VI. Not even need to set data rate or any triggering, or stream the data. It is just one time single point send/read the voltage.

The second function is more complex. It need to trigger a different device (a AWG not on cRIO) to send out a arbitrary waveform, then cRIO will be trigged by a voltage from ADC to start record many data points same time cut off the gate signal to the AWG. This is totally different from the first function, this one require triggers, timing and FIFO to transfer the data.

In the first function, both ADC and DAC are running in continuous mode, PC labview program will just read/send one voltage point as needed, no timing, no triggering really. If I want to switch from the first function into the second, the ADC has to be carefully reset to trigger mode, and the data has to be send through the FIFO channel.

I am thinking to put the first function into two FPGA loops such that RT VI can control the DAC to send one voltage point, then in the second loop to control the ADC. Then the second function with other loops. To control the FPGA vi to switch between the two functions, I will also need a big loop which contains the above loops. 

Anyway, it sounds complex to me, I am wondering if there is better solution. Maybe I should just let the RT VI to reload the two different FPGA VIs.

[gy10c · Accepted solution]

My current understanding now is that I can just use the RT VI to load and unload different FPGA VIs with different functions.

My guessing is that the FPGA bitfile will be flashed into cRIO one time, then the load/unload is all about RAM in the FPGA. It should be no harm of doing so.