cRIO implementation for multiple configurations

[Garord]

Dear All,

I have a project that will consist of two different configurations: the first will require precise control and the second will require only DAQ at various sample rates. These two configurations will each have a completely different set of sensors/electronics, and testing will never have to be done concurrently. I am planning on using one cRIO with C-Series modules that will be applicable to both, and then simply swapping out the breakout board for each C-Series module depending on the testing configuration (the C-Series modules will be enough to cover all the signal types in both configs). If I was using a cDAQ, I would simply have two different VI's - how would this best be implemented with an FPGA-base cRIO? I plan on using the FPGA for the first configuration only. Would I need two bitfiles and have to recompile every time I switch testing configs? 

Any help would be greatly appreciated!

[ZYOng]

As long as you are not swapping the C Series modules, you can keep the same bitfile and change the RT VI for different configurations. Most of the module configurations can be accessed programmatically.

Alternatively, you can create and compile more than one FPGA VI and bitfile. Just create multiple FPGA VI and build spec.

[Garord]

ZYOng,

Thank you very much for the reply. So if I am understanding correctly, we can have one bitfile but multiple RT VIs for different configurations that utilize the same C-series modules the FPGA uses with that respective bitfile? 

[ZYOng]

You can have more than one separate RT VI and more than one FPGA VI in a single project or multiple projects. Only one RT VI and one FPGA VI can be loaded at a single time.

[Garord]

And even if the FPGA has a certain bitfile loaded onto it I can use a different RT VI with different functionality of C-series modules? Here are my configurations:

Configuration 1: High-speed control, C-series digital output card will be controlling relays (through FPGA) and analog output card will be controlling pressure regulator

Configuration 2: Basic DAQ, C-series digital output card (same as above) will be controlling solenoid valves and analog output card will be controlling a fan 

[ZYOng]

The FPGA bitfile is flashed to the FPGA chip when Open FPGA VI Ref is called. Thus you can load different bitfiles at any time.

If two FPGA VI have the same front panel items, you can use more than one RT VI to load them, even if the underlying logic is different. However, if the front panel items are different (even just different names), your RT VI will be broken from the missing items on the Read/Write FPGA IO node.