customized counter totally independent of the on-board clock period at a FPGA board PCI7833R

[IsaacLescano]

Hello,

I have a NI FPGA board PCI-7833R to use on my project. I know that gates inside the FPGA are very fast. I need to make a customized counter that use and external clock applied at DIO0 and an Enable digital signal applied at DIO1. I need this counter be totally independent of the on-board clock (top-level clock). Which means that I need that the digital signals at DIO0 and DIO1 not to be passed to a register, neither sampled or clocked by the on-board clock. I guess that is not possible; but since I still have some hope that it could be done, I need a confirmation. Is it possible to make this kind of counter or not?

I want to do a loop similar to the one shown in attached figure counter_loop.jpg

And I expect a gate level equivalent like the one shown in attached figure counter.jpg that will work at any frequency value from a external clock (example 76MHz, 36MHZ, 250MHz).

If it where possible, I would like to know what is the hardware configuration at gate level (gates and flip-flops) equivalent to the figure counter_loop.jpg

Thank you very much,

Isaac Lescano

www.UTSI.edu

[DuffmanSays]

Hello Isaac,

Unfortunately I will have to confirm your suspicion; the application that you have discussed is not possible with our R-series cards. First of all, the DIO lines are limited by the rate at which the onboard oscillator can poll those lines. Thus with the FPGA's 40MHz onboard clock, you would want a digital pulse width of at least 25ns to guarantee that the DIO rising edge is detected. Additionally, it is not possible to provide an external clock in place of this 40MHz onboard clock to increase the rate at which the digital lines are read. In any case, you would also not have access to the specific gate configuration generated by the LabVIEW FPGA compile process. While I know it was not good news, I hope this was the information that you were looking for! Have a great day.

Mike D.
National Instruments
Applications Engineer

[IsaacLescano]

Can I use a direved clock of 200MHz instead of the 40MHz onboard clock in a PCI-7833R card to have the DIO sensed every 5ns in order to detect digital pulses of 6ns or 7ns?

Thank you,

Isaac

[DuffmanSays]

Hello Isaac,

Unfortunately you cannot use a derived clock of 200 MHz for your digital input operation. While this derived clock can be used to create a clock domain at the rate you specify, input and output operations cannot be used in a clock domain that is faster than the 40 MHz oscillator. With the given timing requirements, there will not be any method by which you can read these digital signals with this 7833R card.

Mike D.
National Instruments
Applications Engineer

[DuffmanSays]

Hello Isaac,

I just wanted to clarify a mistake from my last post. I was incorrect when I mentioned that you cannot use I/O within a clock domain that is faster than 40 MHz. This is actually possible – the DIO node must be contained within a single cycle timed loop. That being said, there will most likely be signal integrity issues when reading or writing to digital lines that quickly. As a rule you can expect 20 MHz of digital bandwidth from this card. Your code will compile when clocking your I/O at a faster rate, but the accuracy of the reading will be questionable when exceeding this practical limit. Please let me know if I can provide any further clarification. Thanks,

Mike D.
National Instruments
Applications Engineer

[IsaacLescano]

Hello,

I have some doubts. The specifications web page http://sine.ni.com/nips/cds/view/p/lang/en/nid/202007 says the following for the counters:

Counter/Timers
Number of Counter/Timers	96
Resolution	64 bits
Maximum Source Frequency	80 MHz
Minimum Input Pulse Width	12.5 ns
Logic Levels	TTL

It says 12.5ns resolution. How do can I program to get this counter? Can I get this 80MHz counter with the programming loop shown in the attached image counter.jpg

[DuffmanSays]

Isaac,

I am currently in the process of clarifying this specification. This specification is not listed in the product manual as I would expect it to be, but I will determine if there may be some reason that the counter input can be reliably clocked at this rate. In any case, the code from the figure would implement a counter that will count any detectable digital events. I will verify that a digital pulse width of 12.5ns is a signal that can be reliably detected by this hardware.

Mike D.

[DuffmanSays]

Issac,

I was able to clarify this specification that is listed on our site but not in the manual. Basically we recommend a digital bandwidth of 20MHz for reads and writes. At this rate, we can guarantee that the signals you generate and read are accurate and that you do not need to consider signal integrity issues. The board actually can handle much faster than this rate, and so a counter can technically read a pulse of 12.5ns width. But please keep in mind that at this high rate, you will need to pay close attention to your signal integrity. For this case, you want to achieve sharp edges on your digital signal and accurate digital logic levels. I hope this addresses your question. Please post back if I can provide any additional assistance. Thank you very much for your time.

Mike D.