displaying a digital clock signal on a oscilloscope

[Naso]

Using LabVIEW 8.0 and a 7811R FPGA module in a PXI - 1042Q chassis.   Trying to generate a digital clock signal for an ADC board from the FPGA.

I have used a timed loop to generate true/false boolena values stored in a shift register, and than I connected those to a DO to use it as a digital clock signal for the ADC board.  Well, I wanted to verify that I am getting a digital signal out, so I connected the DO to a oscilloscope, and I am getting nothing there!
I have an indicator inside the loop that flashes at the clock speed (on the host VI), which tells me that the boolean values are changing, but for some reason the oscilloscope got nothing.

I think this is the way to generate a digital signal since there aren't any other functions I found useful.  Is there something else I need to do to the boolean values in order for them to generate the digital signal?

I would appreciate any input on the matter.

[Naso]

OK, actually I used two methods to generate my digital signal - one with a timed loop, and one with a while loop and a loop counter.

I am finally getting the digital signal on the oscilloscope using the while loop; the problem was fixed once I moved the DIO inside the while loop.  However, this way I can generate a signal with a maximum frequency of 1.0MHz (with a 1 microsecond wired to the loop counter).  This is not enough since I need a 10MHz clock signal.

The timed loops give me a compile error if I put the DIO inside the loop; so, this method is giving me trouble as well.

Here are the questions:
1. With the while loop and loop counter, can I wire decimal values to the loop counter which will also be accepted by the loop counter?  I need a 0.1 microsecond period for 10MHz.
2. Can I somehow avoid the compile error using the timed loops?  If this is possible, I can easily generate the desired clock.

It's a long description of the problem, but I tried to present it clearly.

Thanks.

[Efosa O.]

Naso Hello.

You are correct in the way you are generating your digital signals.

1.) In your while loop, you can place a loop timer in the first frame of a sequence structure and configure it as ticks. 1 tick equals 40MHz. So 4 ticks will equal 10MHz. LabVIEW FPGA will only compile if it can actually run that loop in 10MHz. If it cannot, it will give you compile errors.

2.) Yes you can avoid compile errors using timed loops. What errors are you currently getting when you use the timed loops? Timed loops in FPGA do not currently support arbitration. Right click on your FPGA I/O node and click on Properties. In the arbitration fields, choose "Never arbitrate." Take a look at this Knowledge Base and please post if you are still having errors.

[jdigiova]

One point of clarification.  The normal while loop using a loop timer to control the rate will not give you a compile error if the loop cannot execute in the rate you specify.

For instance, if you set the loop timer to take 4 ticks, but the code within the loop takes 10 ticks, than the loop will actually run at 10 ticks.  However if you change the loop timer to take 15 ticks and the code with the loop takes 10 ticks, than the loop will run every 15 ticks.

You will however get compile errors if you cannot execute code in a Timed Loop within a single clock cycle.  This occurs generally if a function takes multiple cycles to execute, or has arbitration.  As Efosa said the IO in the Timed needs to have the arbitration turned off in order to be able to run in a SCTL.

Regards,

Joseph D.

[Naso]

yeah, I used ticks instead of microseconds, and I got the frequency up to 5MHz (for 1 tick), I guess that's as fast as the loop executes.

I actually found that the OUT connector in the back of my chassis (PXI - 1042Q) provides a clock signal of 10 MHz at 2 V_p-p.  Oh well, thanks for the input, and I will keep the compile error document, might come in handy later.