Good morning.
I want to develop a FPGA DAC interface. The DAC chip is not important because most of them are more or less the same. The problem is that I have to implement this design in VHDL.
Firstly, I’ve implement a simple, functional VHDL module that in simulation work’s fine; after, I’ve imported this module in LabVIEW, using IP Integration Node. I build the project in order to test the VHDL module, and I get an Error : ERROR: Place:1136 - This design contains a global buffer instance... . For this error, the Xilinx recommends to use ODDR2 primitive. I did not introduce this primitive before, because I assumed that LabVIEW will do that. I introduced this primitive in module, rebuild the project, another error appears (ERROR : Place:1206 - This design contains a global buffer instance…) . In this point I said: OK .. it’s something strange here.
And after, I thought to build a VHDL module that only generate a clock on a pin; I start with something simple, and let LabVIEW decide what to use; I build the project, same 1206 error appears; I introduce the ODDR2 primitive (according to Xilinx), another error appears … ERROR: Pack:2530 - The dual data rate register…(photo 1)
In this point, I went back to Xilinx ISE to see if this simple module really works or I do something wrong. The same VHDL module I use, with ODDR2 instantiation, build the project in ISE 14.3, everything is ok (photo 2). I go in ISE 13.4 (that NI FPGA uses), the project also is a success (photo3).
So, the question is, how can I generate a clock on a pin in LabVIEW, using VHDL programming? Or there is a bug?
Best regards,
Felix
Software used:
LabVIEW 2012
NIFPGA 2012 SP1
Target platform
SbRIO9606 + NI 9694 or SbRIO9606 + NI 9683
Xilinx References:
http://www.xilinx.com/support/answers/35032.htm <-the most useful one, from my opinion
http://www.xilinx.com/support/answers/33025.htm
