fpga compile stuck, no errors

[Brian_Christopher]

Hello,

I have written a program in LabVIEW FPGA 8.6.1 (I have written several, this is my newest one). When I execute it on the development computer it seems to run fine without any errors. When I try to compile it, however, it always stalls on this part:

"Analyzing generic Entity <arraycollect_0072> in library <work> (Architecture <rtl>)."

It doesn't feeze (the compiler is still updating the time and you can see it trying to work). It just doesn't progress any further than that point. Does anybody know by chance what might cause this? I know it may be a little vague, sorry. Thanks!

[Brian_Christopher · Accepted solution]

Nevermind, I figured it out. I had an Analog Input Node inside of a For Loop. This input wire (i.e., data wire coming out of the Analog Input Node) was connected to an auto-index tunnel on the For Loop. I just disabled auto-indexing on the that tunnel and everything seems to compile fine now.

[Emmanuelol]

i have some code, who works when i simulated the system, and also every subVI can compile, but when i put all together, the compiling in the 5 step is stuck, never say if something is wrong, any idea¡?

thanks