fpga programing cRIO-9014

[nowoxi]

Hi,

I am trying to configure my cRIO-9014 to generate 2 differenct PMW with varying duty cycles at the same time. One of the PMW should be analogue with voltage range 0 -1 and the other digital. It was easy to design a Pulse generator with fixed duty cycle but changing the duty cycle in realtime was a little of a challenge. Eventually I used the state to control pushing the next variable to the FPGA from the host. That worked well for one of the Pulses but seems to not work well for the second pulse. The FPGA seems to miss some pulses at the start when i check the oscilloscope am using.

Could someone advice me on how I could go about programming labview in a better way so the output of the cRIO is more reliable and always starts and stops from where expected.

[nathand]

Can you be more specific about the problem? You wrote, "That worked well for one of the Pulses but seems to not work well for the second pulse. The FPGA seems to miss some pulses at the start when i check the oscilloscope am using." Which is the first pulse, and which is the second? Or, which one is working, and which one isn't? How many pulses do you "miss"? Are the initial FPGA values the same as the ones you're setting from the host, or are they different? The FPGA code may start running before the host writes values to the FPGA front-panel controls.

It would be a good idea to put a wait or other timer inside the host loop, to prevent it from running as fast as possible and allow the processor time to run other tasks.

[nowoxi]

Thank you Nathand

I measure the output with an oscilloscope from the FGPA and not with the front UI.

To control the pulse duration I have 4 arrays 2 for controlling high pulses and 2 for low pulses. The length of the arrays is the total number of pulses i expect. I have 2 loops in the FPGA that control the generation of the pulses. One of the pulses controls a digital and an analog pulse which responds well( Analog modulator and shutter). The second controls a single digital pulse(Digital Modulator). When I start the VI in the host the output on the scope for the 1st loop works fine but that of the second is definiately not what was expected. It seems random and the geenrated pulse dont have much correlation with the array.

I hope this is a little clearer.

[nathand]

From your comments, I assume that you are seeing the "bad" behavior with a different Host VI than the one you uploaded. Does your FPGA VI generate the digital pulse correctly using a simple test host like the one you uploaded? Are you certain that the problem is the FPGA, and not your real Host VI? Can you upload the code you are actually using, instead of one that doesn't match what you describe?

[nowoxi]

That VI was the wrong one. Didnt realize i uploaded the wrong one thank you. It shoudl be the host_selftimer.vi.

Yes it generated digital pulse correctly using the simple test host. I am not certain the source of the probem. I Programmed both loops and both array sources the same way.

[nowoxi]

Another file

[nathand]

The first problem I see is that dutyCycle_Control.vi contains globally-initialized feedback nodes and is not reentrant, so you only have one instance of it. The feedback nodes are sharing data between the two sets of pulses. While I haven't deciphered exactly what your code is doing, that could cause problems. A quick fix is to set the vi to reentrant execution with pre-allocated clones in VI properties, under the execution category.

However, I'm pretty sure you could rewrite this to be simpler and more reliable. For example, you could use a pair of DMA FIFOs (one per pulse channel) to transfer the entire array at once. The FPGA would simply read an element off the FIFO and use that as the wait timer value. Each time you read a new element off the FIFO, invert the output. There are few more details to work out, but that is one basic approach you could take.

Again, loops on the host side should contain some kind of timing mechanism such as Wait (milliseconds) so that the loop doesn't spin as fast as possible and prevent other tasks from running.

[nowoxi]

Thank you Nahand, will try that and get back to you. I appreciate your help.

[nowoxi]

Pre-allocating instances worked like a charm. The digital modulation now startsas it should. Though i just noticed the analog modulation and shutter in the second loop tend to have about 50ms delay before the pulse starts.

I would read up on the DMA FIFOs it sounds like a much better idea.