fpga timing problem

[Engbrecht]

In my application I have a flat sequence with a Loop Timer in the first frame and a couple of sub vi's in the second frame.  As I have been building one of the sub vi's I have started to get a timing violation error when I compile.  The loop timer is set to 4 ms.  However, the timing violation says I can only reach a clock speed of 22 MHz instead of the desired 40 MHz. 

The compilations seems to be requiring the sub vi to run in a single clock cycle while I only need it to execute in 4 ms.  The sub vi has no timing loops, it simply reads in some data and then does some calculations on it.

Must my sub vi run in a single clock cycle?  Can I change that requirement if it is the case?

I am running a single cycle timing loop in parrallel with this sequence, is that affecting the requirements on the vi's within this sequence.

Any help is appreciated,

Thanks,

Jason

[Christian Mergl]

Hi Jason,

A Timing Violation has nothing to do with a loop timer.

It just says that either your whole code or a certain part of your code can not be executed as fast as you want it to execute, in terms of the FPGA Base Clock. So there are two possibilities, your whole code can not execute with the 40MHz clock, or a SCTL (Single Cycled Timed Loop) can not execute with 40MHz.

You will need to check the compile report with the timing violation to see if its your code in general or if it points to a certain loop, then you either change the Base Clock of your FPGA or you create a derived Clock for the respective SCTL. Both can be done in the project.

In your post it seems to me that you mix up some stuff. You should think about attending a FPGA or cRIO Class at NI.

Christian

Message Edited by Christian_M on 05-18-2010 01:55 AM

[Engbrecht]

Christian,

Thanks for the help.  Just so I'm clear.  When working in fpga, the entire vi (and its sub vi's) must run in a single clock cycle?  I haven't seen that in any documentation so it's a confusing point.

Thanks for the help, I can make this work.

Jason

[Christian Mergl]

"When working in fpga, the entire vi (and its sub vi's) must run in a single clock cycle?"  -> NO, No, no....

I'm sorry if I wasn't clear enough.

So whatever you want to run in a SCTL musst be able to run in a single clock cycle. And only in an SCTL!

The FPGA VI itself, needs whatever time for its execution.

But sometimes your code might become very complex so that an execution with a certain Clock Rate is not possible.

Then you need to reduce the base clock rate for the whole FPGA.

Christian