how can i change fpga clock for whole code

[ceee]

Hi i'm new at labview and using 8.6 demo(real time and fpga modules).

i developed some codes for practise and want to change clock freq to 200MHz from 40M for all codes.

i mean how can i use derived clock for all my vi.

[WillD · Accepted solution]

You create a derived FPGA clock from the "40MHz onboard clock" in the project manager.

Then in the properties for the FPGA you can select "Top Level Clock".  The top level clock for the FPGA can only be the following: 40MHz, 80MHz, 120MHz, 160MHz, 200MHz

[ceee]

PAR done!

ERROR:Xflow - Program par returned error code 31. Aborting flow execution...

when i use 200mhz as fpga clock i'm getting this error after compilation.

is there a way to use fpga other then 40mhz. and i dont want to use timed loops because i am using

loops inside loop.