how to convert array of cluster to array of word?

[crossrulz]

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fanwel wrote:How can I send the dwt coefficients to the host one by one?

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I would use a DMA FIFO to send the coefficients.  Is each coefficient supposed to be a single 16-bit word?

[fanwel]

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@crossrulz wrote:

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fanwel wrote:How can I send the dwt coefficients to the host one by one?

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I would use a DMA FIFO to send the coefficients.  Is each coefficient supposed to be a single 16-bit word?

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First, yes I use a DMA FIFO to send the coefficients. Second, no it not supposed to be a word 16 bit because I want to use the dwt coefficients back to make the inverse dwt at the host. What suppose or exact data type that I need to use to send the coefficients to the fpga vi? Thanks for quick reply

[fanwel]

Anyone help me please?

[nathand]

Let me start by saying I don't know anything about the DWT algorithm, so I don't understand the details of what these coefficients mean.

Are you asking how you can transfer the "dwt coef" structure to the FPGA?  Why are you using this particular structure?  You can't use it on the FPGA as is, because all arrays on the FPGA must be fixed-length.  How many elements are in the overall array, and in each array inside the cluster?

How does the FPGA use this set of coefficients?  On the FPGA, how are you planning to take the data from the FIFO and convert it to a usable format?  You might want to use several front-panel controls to pass this data, instead of a FIFO.  You could pass the array elements one at a time using a handshaking approach (set one control indicating which index to update, one for the value itself, and a boolean indicating when a new value is ready to read).

[fanwel]

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@nathand wrote:

Let me start by saying I don't know anything about the DWT algorithm, so I don't understand the details of what these coefficients mean.

Are you asking how you can transfer the "dwt coef" structure to the FPGA?  Why are you using this particular structure?  You can't use it on the FPGA as is, because all arrays on the FPGA must be fixed-length.  How many elements are in the overall array, and in each array inside the cluster?

How does the FPGA use this set of coefficients?  On the FPGA, how are you planning to take the data from the FIFO and convert it to a usable format?  You might want to use several front-panel controls to pass this data, instead of a FIFO.  You could pass the array elements one at a time using a handshaking approach (set one control indicating which index to update, one for the value itself, and a boolean indicating when a new value is ready to read).

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Dear nathand,

Actually I get the project from NI example finder ( image compression using dwt). Then, I modified the vi because I try to run it in fpga. I realise this is not an easy works, but I need to do it. Is it possible?

[nathand]

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@fanwel wrote:

Actually I get the project from NI example finder ( image compression using dwt). Then, I modified the vi because I try to run it in fpga. I realise this is not an easy works, but I need to do it. Is it possible?

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I do not have that example; I might not have the right toolkit installed.  Were you able to compile the FPGA code?  The coefficients data structure will not work in FPGA (because arrays need to be fixed-size).  It is probably possible to do the processing on the FPGA, but it is not as easy as taking an existing example and moving it to an FPGA target.  Can you share your FPGA code?  Why do you need to do this processing on the FPGA?

[fanwel]

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@nathand wrote:

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@fanwel wrote:

Actually I get the project from NI example finder ( image compression using dwt). Then, I modified the vi because I try to run it in fpga. I realise this is not an easy works, but I need to do it. Is it possible?

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I do not have that example; I might not have the right toolkit installed.  Were you able to compile the FPGA code?  The coefficients data structure will not work in FPGA (because arrays need to be fixed-size).  It is probably possible to do the processing on the FPGA, but it is not as easy as taking an existing example and moving it to an FPGA target.  Can you share your FPGA code?  Why do you need to do this processing on the FPGA?

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Dear nathand,

I not use coding for the fpga implementation and of course I want to avoid to use it. I only use Labview to design the architecture,compile and download to fpga. I want to do this processing on the fpga for image compression application. Moreover, I want to analyse the performance of the system (fpga is the best hardware prototyping board for image compression application). Can you get it? How can I can do this? Thanks for response

[nathand]

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@fanwel wrote:

I not use coding for the fpga implementation and of course I want to avoid to use it. I only use Labview to design the architecture,compile and download to fpga. I want to do this processing on the fpga for image compression application. Moreover, I want to analyse the performance of the system (fpga is the best hardware prototyping board for image compression application). Can you get it? How can I can do this? Thanks for response

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I'm sorry, I don't understand what you wrote here.  What do you mean by, "I not use coding for the FPGA implementation"?

I think in your original question you wanted to ask, "How can I send these coefficients to an FPGA?"  Is that correct?

You cannot use the existing data structure (an array of clusters containing arrays) on the FPGA, so I am trying to understand why you want to transfer it and how the FPGA will use those values.  With that information it should be possible to suggest a solution.  You need to have the FPGA code written or at least a good idea how it will work before you can move forward.

[fanwel]

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@nathand wrote:

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@fanwel wrote:

I not use coding for the fpga implementation and of course I want to avoid to use it. I only use Labview to design the architecture,compile and download to fpga. I want to do this processing on the fpga for image compression application. Moreover, I want to analyse the performance of the system (fpga is the best hardware prototyping board for image compression application). Can you get it? How can I can do this? Thanks for response

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I'm sorry, I don't understand what you wrote here.  What do you mean by, "I not use coding for the FPGA implementation"?

I think in your original question you wanted to ask, "How can I send these coefficients to an FPGA?"  Is that correct?

You cannot use the existing data structure (an array of clusters containing arrays) on the FPGA, so I am trying to understand why you want to transfer it and how the FPGA will use those values.  With that information it should be possible to suggest a solution.  You need to have the FPGA code written or at least a good idea how it will work before you can move forward.

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Dear nathand,

Sorry because make you confius with my problems. Yes you are right, I want to know how to send the dwt coefficients into fpga. The fpga design is as I attach before. What I mean by "not use coding for fpga implementation" is I'm not writing the code (vhdl code), I just do the design in LabView and LabView will automatically convert it into vhdl code later. Thanks for quick response

[nathand]

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@fanwel wrote:

Sorry because make you confius with my problems. Yes you are right, I want to know how to send the dwt coefficients into fpga. The fpga design is as I attach before. What I mean by "not use coding for fpga implementation" is I'm not writing the code (vhdl code), I just do the design in LabView and LabView will automatically convert it into vhdl code later. Thanks for quick response

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Is the VI that you attached earlier, DWT.vi, the VI that will run on the host, or on the FPGA?  I thought it was on the host.  It CANNOT run on the FPGA.  If this is not your FPGA VI, could you attach the correct VI?  If this is the VI that intend to run on the FPGA, then you need to rewrite it, limiting it to functions that the FPGA environment supports.