04-15-2013 10:43 AM
Hello:
I am working with the FPGA in the CRIO and I would like to synchronize some loops inside the FPGA code (for start everyone at the same time), I thought that the best idea is used timed loops with a common clock, but I want to carry out these loops at 1 KHz and the the closest clock that can I derived from the FPGA is 2.5 MHz, how could I create a clock of 1kHz?
Or maybe another for synchronize these loops?
Thanks in advance!
Regards
Alvaro
04-15-2013 10:44 AM - edited 04-15-2013 10:47 AM
04-15-2013 10:57 AM
The problem is that in the timed loop of the FPGA I can´t establish a desired period, I can ony select a certain clock.
04-15-2013 11:00 AM - edited 04-15-2013 11:04 AM
04-15-2013 11:07 AM - edited 04-15-2013 11:10 AM
04-15-2013 11:20 AM
If I put a 1 ms in the a wait of the loop it will give a return late, because the loop execution takes a certain time plus the 1 ms of the wait, so at the end my loop will be carried out in more than 1 ms. And also the loops will not being synchronized because the different loops take different times for the execution, a loop that takes 0.001 ms will be execute the secont time at the time 1.001 (1+0.001) and a loop that takes 0.002 ms will be executed at the time 1.002 ms, isnt it?
In the configuration of the time loop only appears the avaliable clocks(I attacht screen capture).
Regards!
04-15-2013 01:10 PM - edited 04-15-2013 01:12 PM
You are not required to use a timed loop for what you are trying to do. If you feel you MUST use time loops you can use them and let them run faster. Do a cacluation of time elapsed, then when 1 ms is up, send a software trigger (see section #2) to your other loop telling it to execute. You could also do this with a digital output instead. Then reset your timer and do it again.
Please, do a search as was suggested
04-15-2013 04:31 PM
Personally I like to do this using a single-cycle timed loop containing a case structure. Count until you reach the right number of ticks for the desired period, then reset the counter to 0. Put your logic inside the 0 case (or, if timing doesn't allow all the logic to fit in one loop cycle, spread it across several cases).