I'm doing realtime signal processing, and LMS system identification
obtain signal from microphone and emit sound from speaker
most convolution process is conducted in RT
So i send data from RT to FPGA
not vector just sample data
problem is because sampling rate of Timed Loop in RT and Data rate of NI c series is not match slightly
the system identification FIR filter is not converge.
while processing, the coefficient is slowly move toward left. i suspect the gap of sampling rate between RT and FPGA.
but when i run with Full speed of Data rate, the problem could be overcome.
however there is a big problem. because i send a sample data from RT to FPGA, if data rate of FPGA is 3times bigger than RT.
Speaker emit sound like 1 0 0 2 0 0 3 0 0 2 0 0 1 0 0. original signal is 1 2 3.
So i have to interpolation in FPGA
I know i can you resampler VI. but i don't know how i use is VI correctly......
please show how could i upsampling in FPGA
