may i know where exactly i have gone wrong

[irfan789]

when i run this code my pid is giving the very high output values from the controller....

i am trying to give disturbance manually and expecting controller output

here is the attachment...

acquring the speed of the fan in FPGA mode and calling the FPGA vi in RT of the target

and over RT i have made a PID control

and manual diturbance is given through FPGA 

[GerdW]

Hi irfan,

you should learn to give more descriptive thread titles…

- I don't think you need a TWL in the RT part when it comes to have a loop running once per second…

- I don't know from the picture if the FPGA counter loop will ever stop as that depends on a comparison of loop iterator with some "y" input…

- Why don't you put the AO output node in it's own parallel loop? Why have counter and AO in one loop?

- We don't know anything about your PID parameters/settings nor do we know anything about the behaviour of your "fan". So how should we judge on the implementation of your PID algorithm?

[JÞB]

I really hate ignoring students....Gerd has given you some pointers.  i'll give you another....... post your vi (not a picture) and save some values as default.

[irfan789]

fortunately my code is working 

but i made few corrections

i am gonna post them now 

and i just need clarification where  to keep my PID loop in RT or FPGA

need bit info how to tune my pid knowing that there are method to tune pid like cohen coon and ziegler nichols....

by the way those were not just pictures sir..

those are snippets which can be dragged to block diagram and used as a code...

[Mashfique]

Hello Mr Gerd

here's few explanation to the following

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I don't think you need a TWL in the RT part when it comes to have a loop running once per second…

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answer :yes of course i can replace a TWL with normal while loop and keep some delay    but i used TWL in  order to maintain the same rate of execution as RT gets  INPUTs from FPGA which updates my speed for every one sec

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 I don't know from the picture if the FPGA counter loop will ever stop as that depends on a comparison of loop iterator with some "y" input…

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answer: yes it does stop for the value y=40000000(40*10^6) 

for every one sec fpga performs "y" number of iterations and counts number of pulses(digital) per second with that i get my speed

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parameters are avalabcle here.

http://forums.ni.com/t5/LabVIEW/PID-is-not-returning-any-output/m-p/2744950#M810826

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