measuring frequency of analog input acquired thru FPGA i/o

[Vijay Chand]

Hi all

I am using the PXI-7831R device (RIO), and i am acquiring analog signals for my application (Sine waveform).

Now what i need to do is, to "find out the frequency of the sensed sine wave analog input".

I tried using the "extract signal tone information.vi" and the "analog period measurement".

But somehow both are not giving the required result.

Can someone help me with a link to some examples or tutorials! Or if someone has worked on the same in an easier way....please help me out of this.

Thank You

Vijay Chand Ganti

[Henrik_Volkers]

It would be helpful if you post a png of the signal and the vi (best with some real data in it (capture  datat and then make current values default.

Additional information would also be helpful: is it a known frequency (maybe due to known excitation?) and needed bandwidth ...

[Lucither]

Hi,

Maybe you are picking up some noise from your source that is effecting the reading. If you know roughly the frequency you are getting perhaps you could filter the waveform first before trying to acquire the frequency.

Just a thought,

Regards,

Lucither

P.S Could you post some code

[Vijay Chand]

hi

Thank you for ur replies....

My signal is a sine wave of 3V(p-p) amplitude and 50kHz frequency....

I used the method and conversion(period to frequency) employed in the "Measuring signal period" example in the NI example finder.

I

[Vijay Chand]

Hi

I am attctching the snapshots of my project.

There are two VI's,one on the FPGA and other on the host(PXI).

I am using the "analog period measurement" to measure the period of the SIne wave(3Vp-p and 50kHz freq) acquired thru the AI0 pin of the FPGA device (7831R).

Then i am manipulating this period and converting into frequency (using some basic math as seen in the snapshot).

The problem is "the value of period is always zero!!".

I dont know,if the problem is with the data types and values of the threshold and hystersis given to the analog period

measurement block!!

Please help me out of this as i am struggling with this for some time now!

Thank you

Vijay Chand Ganti

[JLewis]

Hi Vijay,

You've got a coercion from the Period's U32 output to an I16 indicator. Since the output is scaled up by 2^16, this means you're losing the entire integer portion of your result. (In later versions, it's a fixed-point output, which makes the scaling more explicit and a bit easier to deal with.)

In general, coercions are more serious on FPGA diagrams, so you'll want to carefully study each one and eliminate them when possible.

If you still have problems with the results after fixing the indicator type, please provide a screenshot of the raw acquired waveform along with the threshold and hysteresis values you're using.

Jim

[Vijay Chand]

Hi

Thank you for the insight! I will surely try the same and get back.

Vijay Chand Ganti

[Vijay Chand]

Hi Jim

I modified the data types as identified by you, but still facing the same problem!

The value of period is always "zero" and hence the frequency infinite!

I am giving a 50Khz,3V(p-p) sine wave to the analog input channel, and  tried with different values of threshold and hystersis (ranging from -3000 to 3000).

Can you please identify whats the error!!

I would be very thankful if someone points out what the exact problem is!

I have attatched the front panel of the host program when running.

[xseadog]

Hi

Why is your threshold set at -1000?

According to your FP scaling you will never achieve this value!

Suggest you adjust value to + or - 1.

See if that helps you for anon infinite frequency.

Xseadog

[JLewis]

Hi Vijay,

The Period measurement output is not internally latched and you aren't monitoring the results ready output signal, so I'm guessing that it is actually returning the correct frequency but you just aren't seeing it. You can test that really quickly by putting a conditional probe on the Period result in your host VI, set to pause whenever the result is nonzero.

To catch the result, you can either add a latch on the FPGA (use a Select and feedback node to update the period value only when results ready is true), or pass the results ready signal to the host and handle it there.

Jim