measuring loop timing in simulating mode

[loghmani]

Hi

I wrote an FPGA VI, I want to know the loop timing of my program. The problem is that I don't have the hardware in order to upload the program on it and run the program and using the technique which is used in the below link:

http://www.ni.com/tutorial/14532/en/#toc5

I choosed execution on Development Computer with Simulated I/O, but I think that it does not turn a valid timing for running on the FPGA target because it's now running on the cpu of the computer. Is there any way to measure the loop timing in simulating mode?

Thanks

[loghmani]

Any idea?

[Norbert_B]

The simulation is a lot slower than the real FPGA. So what exactly are you looking for?

Also note that execution speed on FPGA is specified as ticks, which refer to the clock of the FPGA. Most FPGAs are able to run with different clock setting ("overclocking"). Base clock typically is 40MHz, but can be increased by a integer multiple on most targets (80, 120, ...).

So essentially, FPGA code takes "ticks" to execute and the code itself defines how many ticks the code will require all together.

Norbert