memory read method in FPGA regular loop

[gy10c]

Hi,

It says in the NI manual and is shown in labview example: to use the memory read method node in the single cycle timed loop, you have to add feedback nodes to consider the latency.

My question is that if I just use the memory read method in a regular loop in the FPGA VI, do I still need to add the feedback node? In this case should the memory read return data after ticks delay or it has to go through several cycles of the loop?

Thanks!

[ZYOng · Accepted solution]

You don't need the feedback node if you use the while loops. From <LabVIEW>\examples\R Series\FPGA Fundamentals\Data Storage and Transfer\Memory\Memory.vi

[gy10c]

Yes, I see that example!

[UMASO]

Hello, I guess the background of your questions is that you would like to avoid the mandatory feedback node after memory read method.  I agree that the mandatory feedback node after memory read is a bit tedious to handle.  In addition, feedback node after memory read method does not allow you to use "enable terminal".  

Using regular While Loop allows you to write FPGA code in a similar manner to regular LabVIEW; however as you may already notice, it is much less efficient in terms of FPGA resource utilization as well as processing speed/performance.  As far as I remember (sorry I do not have time to test) memory read method does not return results in next clock cycle.  Even if it could return result in one clock cycle, any data transfer mehcanism right after memory method takes at least another clock cycle.  

Personally, I do not use regular While Loop for LabVIEW FPGA programming, unless some situations force me to do so, such as AI/AO IO nodes for R-series / cRIO / other devices.  

Anyways, I think it depends on your requirements for which way you choose.  

1. Simpler programming, but less efficient / performance

2. More like HDL programming, and more optimizable.  

If I went too far with making too much assumptions for your situation, apolozies in advance.  

[gy10c]

Thanks for confirm and clarify the regular loops/single cycled loop.

My application is actually for AI/AO, but as I go further to more complex measurement with feedback I may need to use more HDL like code.

[UMASO]

If it is desired to make delay from AI to AO as small as possible, you should absolutely consider using SCTL.  

Easiest method you may apply is explained in section "USING THE SCTL AS A WAY TO SAVE RESOURCES " in the document below.  

file:///C:/Users/FujiokaOsamu/Downloads/labview_high-perf_fpga_v1.1.pdf

Or you can transfer data between regular while loop and SCTL by FIFO or registers.  

I do not have clear answers which way of below tow accomplishes the minimum delay, but it may worth testing by yourself.  

1. Place one regular while loop and do AI -> Processing by SCTL inside regular while loop -> AO.  
2. Place two regular while loops for AI and AO, and one (or more) SCTL for processing between AI and AO.  Transferring data between loops by FIFO (or may be registers.  )